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drm/amdgpu: query aldebaran gfx_config through atomfirmware i/f

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For ASICs that don't support ip discovery feature, query
gfx configuration through atomfirmware interface, rather
than gpu_info firmware.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2020-11-13 14:35:39 +08:00 • committed by Alex Deucher
parent acdd5b72c5
commit 7159a36e11
3 changed files with 63 additions and 1 deletions
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19
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
View file

@ -500,7 +500,8 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
}
union gfx_info {
struct atom_gfx_info_v2_4 v24;
struct atom_gfx_info_v2_4 v24;
struct atom_gfx_info_v2_7 v27;
};
int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
@ -535,6 +536,22 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
return 0;
case 7:
adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
return 0;
default:
return -EINVAL;
}

4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View file

@ -2188,6 +2188,10 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
gb_addr_config &= ~0xf3e777ff;
gb_addr_config |= 0x22014042;
/* check vbios table if gpu info is not available */
err = amdgpu_atomfirmware_get_gfx_info(adev);
if (err)
return err;
break;
default:
BUG();

41
drivers/gpu/drm/amd/include/atomfirmware.h
View file

@ -1531,6 +1531,47 @@ struct atom_gfx_info_v2_4
uint32_t sram_custom_rm_fuses_val;
};
struct atom_gfx_info_v2_7 {
struct atom_common_table_header table_header;
uint8_t gfxip_min_ver;
uint8_t gfxip_max_ver;
uint8_t max_shader_engines;
uint8_t reserved;
uint8_t max_cu_per_sh;
uint8_t max_sh_per_se;
uint8_t max_backends_per_se;
uint8_t max_texture_channel_caches;
uint32_t regaddr_cp_dma_src_addr;
uint32_t regaddr_cp_dma_src_addr_hi;
uint32_t regaddr_cp_dma_dst_addr;
uint32_t regaddr_cp_dma_dst_addr_hi;
uint32_t regaddr_cp_dma_command;
uint32_t regaddr_cp_status;
uint32_t regaddr_rlc_gpu_clock_32;
uint32_t rlc_gpu_timer_refclk;
uint8_t active_cu_per_sh;
uint8_t active_rb_per_se;
uint16_t gcgoldenoffset;
uint16_t gc_num_gprs;
uint16_t gc_gsprim_buff_depth;
uint16_t gc_parameter_cache_depth;
uint16_t gc_wave_size;
uint16_t gc_max_waves_per_simd;
uint16_t gc_lds_size;
uint8_t gc_num_max_gs_thds;
uint8_t gc_gs_table_depth;
uint8_t gc_double_offchip_lds_buffer;
uint8_t gc_max_scratch_slots_per_cu;
uint32_t sram_rm_fuses_val;
uint32_t sram_custom_rm_fuses_val;
uint8_t cut_cu;
uint8_t active_cu_total;
uint8_t cu_reserved[2];
uint32_t gc_config;
uint8_t inactive_cu_per_se[8];
uint32_t reserved2[6];
};
/*
***************************************************************************
Data Table smu_info structure