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Armv8 FVP/Vexpress/Juno updates for v6.15

Browse source 
The main and bulk of the addition this time is the support for the Arm
 reference Morello System Development Platform (SDP).
 
 The Morello architecture is an experimental extension to Armv8.2-A,
 enhancing the AArch64 execution state with capabilities for fine-grained
 memory protection and scalable software compartmentalization. However
 these changes doesn't add any of the support for security enhancements.
 This is mainly adding device tree support for Morello SDP.
 
 The platform iteslf is shipped with ACPI firmware. However, since the
 ACPI bindings for GPU, DPU, I2C, I2S,..etc are not well defined or not
 provided in the shipped ACPI firmware, there is a need for the device
 tree as alternative for the developers focusing on those features.
 
 The CPU is called rainier, the architecture is Morello and the platform
 is Morello SDP board. There is FVP equivalent of the same though they
 are not completely in feature parity with the real hardware.
 
 These changes provide the initial support for Morello SDP and FVP
 platforms.
 
 Apart from this, we have an update to add support for secondary cores
 on Corstone1000 FVP platform.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmfG0LIACgkQAEG6vDF+
 4phFpg/8D35cH6WWpfWWp0L3EILUVUcWRn0X0a4UJ7z2cl4UMn+cu7h2mzk6rT16
 fCVj0Sjuek4AZgVpKT8+3A+GugRAIrmq1teRjfcu34yQFyGh/M95IhAs1ym0RQAN
 r6Ox0dCjHJc78tQ6zstLElbkINnf9FtrXjmOCeu8nNOkWODupDuLwC/sROavHXSD
 Yr6+ACCMBvfAIVQUFa1tC1YOvJH/+wKAjISVFJoB7hNG/VqLLEQNQ15HH/Gp97Vn
 18oj5471GyIsKXiT2a3hnitDKfnRGnxLVRxSOEFGVR8n0D+HNphYQi11fi1CSkio
 HI6WDa3m1QP7CGlIW7PD+qClT7djNLUjcQglIF4+SV3NZWotGRRN6Uk7Bq+G24cS
 jFlXVy3iTfdGwvsnRU6S3WOdHTfjxOeJN6Bei9K262LUkCCl/t7M0q1EKu9twOY+
 L0AZvk+g2kqm64KbxHxrHJYTE64ykpw6AnO1vXIM5xR1ov1/XVrzPTPfIIgI4Tb4
 r99iIxhThXYe/bJ4yW4JKdW7CG6ZeyCVeIV1/MkhztlnsnR4O5EA8orEntQUdLOY
 VB/bHwVWCwvpSGmc928cxVUbfHfq/wyEwYBnEmxclAHug8mcSCgPtH52fhB69VWS
 uZAth1lqztgxS6kKN6TzeYvH2gxTeN5v+DWUgrktNOzIsAFTH4I=
 =QVaZ
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfJwy4ACgkQYKtH/8kJ
 UifGKRAA3Ke0JZLQSnnaSxTMctu+1CqT14m+sZ4ohVmncRPpG6v2mBPIxqxm1ivC
 X1fS2DJOO6/bASyhG9p05psW3zSyWNlsppiw3Sc5GtpuqBOPGbeTcA6WVT0TnMAy
 KrAlmeisql+SBKBNGkv0XW58fAbqeYCR/hPthQoqgHpWMON8lBMQvnx+JiH7IzTH
 /CYt1Fkqm0L1O4vz0lUfdjhdJ79eqvHpkvpdaNZK3mwPe49WVS4hTrgfJeq8B8Pp
 Z0pqmXTIeVfrc1aSKCPoOLNys8vxhTjazXzfto7hCahlUWNWCoPpUryK7MA6qo5f
 aOKP8AwsZhJ0tr4xf1u1kYYcjUDI7sYSTi9g/4oLuTjXTCnmXMIZWO5/fOBn574i
 mx3UK7UD6n/PhNWzgSbJGzWtPzOcaMycvDKLbpuU2UT1YRVUegpoecPApicntt0a
 IfBTEgWvLkpjgeP0AODqiuM26xWbfxdrd9iH9JIIwsoKnHO86/8QlNBqLB9+fHhZ
 9FhAs48Y+C7B4DUOUIXHLD8TYD3zhIjM/sE+BJVGUQvtiFqBgfC9/rZNMMMwxsV5
 jVnzSGbFO0RKSQOJr27lcydRICGaeINmEI+wKVJuQFutAtXf9p9jCbHi744Rz0no
 QSnwB+5p+hZLb9tx+DkIakG/IwscvLbg86/WV3L/IjLV+imHVv4=
 =Pf5p
 -----END PGP SIGNATURE-----

Merge tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt

Armv8 FVP/Vexpress/Juno updates for v6.15

The main and bulk of the addition this time is the support for the Arm
reference Morello System Development Platform (SDP).

The Morello architecture is an experimental extension to Armv8.2-A,
enhancing the AArch64 execution state with capabilities for fine-grained
memory protection and scalable software compartmentalization. However
these changes doesn't add any of the support for security enhancements.
This is mainly adding device tree support for Morello SDP.

The platform iteslf is shipped with ACPI firmware. However, since the
ACPI bindings for GPU, DPU, I2C, I2S,..etc are not well defined or not
provided in the shipped ACPI firmware, there is a need for the device
tree as alternative for the developers focusing on those features.

The CPU is called rainier, the architecture is Morello and the platform
is Morello SDP board. There is FVP equivalent of the same though they
are not completely in feature parity with the real hardware.

These changes provide the initial support for Morello SDP and FVP
platforms.

Apart from this, we have an update to add support for secondary cores
on Corstone1000 FVP platform.

* tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: corstone1000: Add definitions for secondary CPU cores
  MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer
  arm64: dts: morello: Add support for fvp dts
  arm64: dts: morello: Add support for soc dts
  arm64: dts: morello: Add support for common functionalities
  dt-bindings: arm-pmu: Add support for ARM Rainier PMU
  dt-bindings: arm: Add Rainier compatibility
  dt-bindings: arm: Add Morello fvp compatibility
  dt-bindings: arm: Add Morello compatibility
  arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS

Link: https://lore.kernel.org/r/20250304105856.432848-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-06 16:45:49 +01:00
commit 70fcb05fe4
11 changed files with 632 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

35
Documentation/devicetree/bindings/arm/arm,morello.yaml Normal file
View file

@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,morello.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Morello Platforms
maintainers:
- Vincenzo Frascino <vincenzo.frascino@arm.com>
description: |+
The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
ARM's Morello Platforms are built as a research project to explore
capability architectures based on arm.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Arm Morello System Platforms
items:
- enum:
- arm,morello-sdp
- arm,morello-fvp
- const: arm,morello
additionalProperties: true
...

1
Documentation/devicetree/bindings/arm/cpus.yaml
View file

@ -177,6 +177,7 @@ properties:
- arm,neoverse-v2
- arm,neoverse-v3
- arm,neoverse-v3ae
- arm,rainier
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan

1
Documentation/devicetree/bindings/arm/pmu.yaml
View file

@ -67,6 +67,7 @@ properties:
- arm,neoverse-v2-pmu
- arm,neoverse-v3-pmu
- arm,neoverse-v3ae-pmu
- arm,rainier-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
- nvidia,denver-pmu

7
MAINTAINERS
View file

@ -2750,6 +2750,13 @@ F: arch/arm/boot/dts/socionext/milbeaut*
F: arch/arm/mach-milbeaut/
N: milbeaut
ARM/MORELLO PLATFORM
M: Vincenzo Frascino <vincenzo.frascino@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/arm,morello.yaml
F: arch/arm64/boot/dts/arm/morello*
ARM/MOXA ART SOC
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

5
arch/arm64/Kconfig.platforms
View file

@ -374,13 +374,12 @@ config ARCH_UNIPHIER
This enables support for Socionext UniPhier SoC family.
config ARCH_VEXPRESS
bool "ARMv8 software model (Versatile Express)"
bool "ARM Ltd Platforms"
select GPIOLIB
select PM
select PM_GENERIC_DOMAINS
help
This enables support for the ARMv8 software model (Versatile
Express).
This enables support for the ARM Ltd Platforms.
config ARCH_VISCONTI
bool "Toshiba Visconti SoC Family"

1
arch/arm64/boot/dts/arm/Makefile
View file

@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb

26
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
View file

@ -49,3 +49,29 @@
clock-names = "smclk", "apb_pclk";
};
};
&cpus {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};

3
arch/arm64/boot/dts/arm/corstone1000.dtsi
View file

@ -21,7 +21,7 @@
stdout-path = "serial0:115200n8";
};
cpus {
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -29,6 +29,7 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};

77
arch/arm64/boot/dts/arm/morello-fvp.dts Normal file
View file

@ -0,0 +1,77 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*/
/dts-v1/;
#include "morello.dtsi"
/ {
model = "Arm Morello Fixed Virtual Platform";
compatible = "arm,morello-fvp", "arm,morello";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
bp_refclock24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "bp:clock24mhz";
};
block_0: virtio_block@1c170000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c170000 0x0 0x200>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
net_0: virtio_net@1c180000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c180000 0x0 0x200>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
};
rng_0: virtio_rng@1c190000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c190000 0x0 0x200>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
p9_0: virtio_p9@1c1a0000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c1a0000 0x0 0x200>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
};
kmi_0: kmi@1c150000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x1c150000 0x0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi_1: kmi@1c160000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x1c160000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
eth_0: ethernet@1d100000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x1d100000 0x0 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
&uart0 {
status = "okay";
};

157
arch/arm64/boot/dts/arm/morello-sdp.dts Normal file
View file

@ -0,0 +1,157 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*/
/dts-v1/;
#include "morello.dtsi"
/ {
model = "Arm Morello System Development Platform";
compatible = "arm,morello-sdp", "arm,morello";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
dpu_aclk: clock-350000000 {
/* 77.1 MHz derived from 24 MHz reference clock */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <350000000>;
clock-output-names = "aclk";
};
dpu_pixel_clk: clock-148500000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
clock-output-names = "pxclk";
};
i2c0: i2c@1c0f0000 {
compatible = "cdns,i2c-r1p14";
reg = <0x0 0x1c0f0000 0x0 0x1000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dpu_aclk>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
hdmi_tx: hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
video-ports = <0x234501>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&dp_pl0_out0>;
};
};
};
};
dp0: display@2cc00000 {
compatible = "arm,mali-d32", "arm,mali-d71";
reg = <0x0 0x2cc00000 0x0 0x20000>;
interrupts = <0 69 4>;
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
<&smmu_dp 8>;
#address-cells = <1>;
#size-cells = <0>;
pl0: pipeline@0 {
reg = <0>;
clocks = <&dpu_pixel_clk>;
clock-names = "pxclk";
port {
dp_pl0_out0: endpoint {
remote-endpoint = <&tda998x_0_input>;
};
};
};
};
smmu_ccix: iommu@4f000000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x4f000000 0x0 0x40000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
msi-parent = <&its1 0>;
#iommu-cells = <1>;
dma-coherent;
};
smmu_pcie: iommu@4f400000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x4f400000 0x0 0x40000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
msi-parent = <&its2 0>;
#iommu-cells = <1>;
dma-coherent;
};
pcie_ctlr: pcie@28c0000000 {
device_type = "pci";
compatible = "pci-host-ecam-generic";
reg = <0x28 0xC0000000 0 0x10000000>;
ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>,
<0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>,
<0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>;
bus-range = <0 255>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0 &its_pcie 0 0x10000>;
iommu-map = <0 &smmu_pcie 0 0x10000>;
};
ccix_pcie_ctlr: pcie@4fc0000000 {
device_type = "pci";
compatible = "pci-host-ecam-generic";
reg = <0x4f 0xC0000000 0 0x10000000>;
ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>,
<0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>,
<0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>;
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0 &its_ccix 0 0x10000>;
iommu-map = <0 &smmu_ccix 0 0x10000>;
};
};
&uart0 {
status = "okay";
};

323
arch/arm64/boot/dts/arm/morello.dtsi Normal file
View file

@ -0,0 +1,323 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
soc_refclk50mhz: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "apb_pclk";
};
soc_refclk85mhz: clock-85000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <85000000>;
clock-output-names = "iofpga:aclk";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,rainier";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
/* 4 ways set associative */
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <512>;
next-level-cache = <&l2_0>;
clocks = <&scmi_dvfs 0>;
l2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-unified;
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-size = <0x100000>;
cache-unified;
};
};
};
cpu1: cpu@100 {
compatible = "arm,rainier";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
/* 4 ways set associative */
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <512>;
next-level-cache = <&l2_1>;
clocks = <&scmi_dvfs 0>;
l2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu2: cpu@10000 {
compatible = "arm,rainier";
reg = <0x0 0x10000>;
device_type = "cpu";
enable-method = "psci";
/* 4 ways set associative */
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <512>;
next-level-cache = <&l2_2>;
clocks = <&scmi_dvfs 1>;
l2_2: l2-cache-2 {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu3: cpu@10100 {
compatible = "arm,rainier";
reg = <0x0 0x10100>;
device_type = "cpu";
enable-method = "psci";
/* 4 ways set associative */
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <512>;
next-level-cache = <&l2_3>;
clocks = <&scmi_dvfs 1>;
l2_3: l2-cache-3 {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
};
firmware {
interrupt-parent = <&gic>;
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
#address-cells = <1>;
#size-cells = <0>;
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
/* The first bank of memory, memory map is actually provided by UEFI. */
memory@80000000 {
device_type = "memory";
/* [0x80000000-0xffffffff] */
reg = <0x00000000 0x80000000 0x0 0x7f000000>;
};
memory@8080000000 {
device_type = "memory";
/* [0x8080000000-0x83f7ffffff] */
reg = <0x00000080 0x80000000 0x3 0x78000000>;
};
pmu {
compatible = "arm,rainier-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure-firmware@ff000000 {
reg = <0x0 0xff000000 0x0 0x01000000>;
no-map;
};
};
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
ranges;
uart0: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2a400000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
gic: interrupt-controller@30000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */
<0x0 0x300c0000 0x0 0x80000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
interrupt-controller;
#address-cells = <2>;
#size-cells = <2>;
ranges;
its1: msi-controller@30040000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x30040000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
its2: msi-controller@30060000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x30060000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
its_ccix: msi-controller@30080000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x30080000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
its_pcie: msi-controller@300a0000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x300a0000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
};
smmu_dp: iommu@2ce00000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x2ce00000 0x0 0x40000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "gerror", "cmdq-sync";
#iommu-cells = <1>;
};
mailbox: mhu@45000000 {
compatible = "arm,mhu-doorbell", "arm,primecell";
reg = <0x0 0x45000000 0x0 0x1000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
clocks = <&soc_refclk50mhz>;
clock-names = "apb_pclk";
};
sram: sram@6000000 {
compatible = "mmio-sram";
reg = <0x0 0x06000000 0x0 0x8000>;
ranges = <0 0x0 0x06000000 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
cpu_scp_hpri0: scp-sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
cpu_scp_hpri1: scp-sram@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};