From 28ddb755949b996637eb457759edff5de77a474d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 28 May 2025 14:35:48 -0400 Subject: [PATCH 01/31] dt-bindings: soc: Add fsl,imx23-digctl.yaml for i.MX23 and i.MX28 Add fsl,imx23-digctl.yaml for i.MX23 and i.MX28 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/mxs/imx23-sansa.dtb: /apb@80000000/apbh-bus@80000000/digctl@8001c000: failed to match any schema with compatible: ['fsl,imx23-digctl'] Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250528183549.694434-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../bindings/soc/fsl/fsl,imx23-digctl.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/fsl,imx23-digctl.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,imx23-digctl.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,imx23-digctl.yaml new file mode 100644 index 000000000000..3de135a70579 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,imx23-digctl.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,imx23-digctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale mxs digctrl for i.MX23/i.MX28 + +description: | + The digital control block provides overall control of various items within + the top digital block of the chip, including: + - Default first-level page table (DFLPT) controls + - HCLK performance counter + - Free-running microseconds counter + - Entropy control + - BIST controls for ARM Core and On-Chip RAM + - Chip Revision register + - USB loop back congtrol + - Other miscellaneous controls + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx28-digctl + - const: fsl,imx23-digctl + - const: fsl,imx23-digctl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + digctl@8001c000 { + compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; + reg = <0x8001c000 0x2000>; + interrupts = <89>; + }; + From 1c69ba9bf0f3032428e6820bada0bb50016a5db6 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 29 May 2025 16:05:19 -0400 Subject: [PATCH 02/31] dt-bindings: lcdif: add lcd panel related property for imx28 Allow lcd panel related property for imx28 and keep the same restriction for other platform. It is legancy platform and set these property to deprecated. Fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dtb: lcdif@80030000 (fsl,imx28-lcdif): 'display', 'display0' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250529200520.798117-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../bindings/display/fsl,lcdif.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml index 8e3a98aeec32..2dd0411ec651 100644 --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml @@ -71,12 +71,23 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: The LCDIF output port + display: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to display panel + deprecated: true + + display0: + $ref: panel/panel-common.yaml# + deprecated: true + + lcd-supply: + deprecated: true + required: - compatible - reg - clocks - interrupts - - port additionalProperties: false @@ -175,6 +186,12 @@ allOf: properties: dmas: false dma-names: false + display: false + display0: false + lcd-supply: false + + required: + - port examples: - | From 5e61d44d0f4637b7d47dbaa40dd95e1388e3eb18 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 30 May 2025 18:05:42 -0500 Subject: [PATCH 03/31] dt-bindings: display: convert sitronix,st7586 to YAML Convert the sitronix,st7586 binding documentation from .txt to .yaml. Also added a link to the datasheet while we are touching this. Signed-off-by: David Lechner Link: https://lore.kernel.org/r/20250530-devicetree-convert-sitronix-st7586-to-yaml-v1-1-c132b512ec57@baylibre.com Signed-off-by: Rob Herring (Arm) --- .../bindings/display/sitronix,st7586.txt | 22 ------- .../bindings/display/sitronix,st7586.yaml | 61 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 62 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/sitronix,st7586.txt create mode 100644 Documentation/devicetree/bindings/display/sitronix,st7586.yaml diff --git a/Documentation/devicetree/bindings/display/sitronix,st7586.txt b/Documentation/devicetree/bindings/display/sitronix,st7586.txt deleted file mode 100644 index 1d0dad1210d3..000000000000 --- a/Documentation/devicetree/bindings/display/sitronix,st7586.txt +++ /dev/null @@ -1,22 +0,0 @@ -Sitronix ST7586 display panel - -Required properties: -- compatible: "lego,ev3-lcd". -- a0-gpios: The A0 signal (since this binding is for serial mode, this is - the pin labeled D1 on the controller, not the pin labeled A0) -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) - -Example: - display@0{ - compatible = "lego,ev3-lcd"; - reg = <0>; - spi-max-frequency = <10000000>; - a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/display/sitronix,st7586.yaml b/Documentation/devicetree/bindings/display/sitronix,st7586.yaml new file mode 100644 index 000000000000..566aaf1aeac8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7586.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7586.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7586 Display Controller + +maintainers: + - David Lechner + +description: + Sitronix ST7586 is a driver and controller for 4-level gray + scale and monochrome dot matrix LCD panels. + https://topwaydisplay.com/sites/default/files/2020-04/ST7586S.pdf + +$ref: panel/panel-common.yaml# + +additionalProperties: false + +properties: + compatible: + const: lego,ev3-lcd + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + a0-gpios: + description: + The A0 signal (for serial mode, this is the pin labeled D1 on the + controller, not the pin labeled A0) + maxItems: 1 + + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - a0-gpios + - reset-gpios + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "lego,ev3-lcd"; + reg = <0>; + spi-max-frequency = <10000000>; + a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a92290fffa16..a38c18142bd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7825,7 +7825,7 @@ DRM DRIVER FOR SITRONIX ST7586 PANELS M: David Lechner S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git -F: Documentation/devicetree/bindings/display/sitronix,st7586.txt +F: Documentation/devicetree/bindings/display/sitronix,st7586.yaml F: drivers/gpu/drm/sitronix/st7586.c DRM DRIVER FOR SITRONIX ST7571 PANELS From f2d26960e0db8f99708960d86cedb9f1f2e822f7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 2 Jun 2025 10:49:06 -0400 Subject: [PATCH 04/31] dt-bindings: display: arm,pl11x: Allow resets property Allow resets property to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: lcd-controller@40008000 (arm,pl111): 'resets' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250602144906.944866-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/arm,pl11x.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.yaml b/Documentation/devicetree/bindings/display/arm,pl11x.yaml index 6cc9045e5c68..a43c1c9d9113 100644 --- a/Documentation/devicetree/bindings/display/arm,pl11x.yaml +++ b/Documentation/devicetree/bindings/display/arm,pl11x.yaml @@ -78,6 +78,9 @@ properties: If not present, the memory interface is fast enough to handle all possible video modes. + resets: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/$defs/port-base additionalProperties: false From d205b07e7e8501fd2a50976ad4b54eed31c556b2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 2 Jun 2025 11:28:13 -0400 Subject: [PATCH 05/31] dt-bindings: display: convert himax,hx8357d.txt to yaml format Convert himax,hx8357d.txt to yaml format. Additional changes: - add spi parent node in examples. - ref to spi-peripheral-props.yaml. - change himax,hx8357a to himax,hx8357 to align driver and existed dts. - add himax,hx8369a and fallback to himax,hx8369. - allow spi-cpha and spi-cpol to align existed dts. - add im-gpios for interface selections. - add reset-gpios. Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250602152814.949671-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../bindings/display/himax,hx8357.yaml | 78 +++++++++++++++++++ .../bindings/display/himax,hx8357d.txt | 26 ------- MAINTAINERS | 2 +- 3 files changed, 79 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/himax,hx8357.yaml delete mode 100644 Documentation/devicetree/bindings/display/himax,hx8357d.txt diff --git a/Documentation/devicetree/bindings/display/himax,hx8357.yaml b/Documentation/devicetree/bindings/display/himax,hx8357.yaml new file mode 100644 index 000000000000..34c3b89bf003 --- /dev/null +++ b/Documentation/devicetree/bindings/display/himax,hx8357.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/himax,hx8357.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX8357D display panel + +description: + Display panels using a Himax HX8357D controller in SPI + mode, such as the Adafruit 3.5" TFT for Raspberry Pi. + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - items: + - enum: + - adafruit,yx350hv15 + - himax,hx8357b + - const: himax,hx8357 + - items: + - enum: + - himax,hx8369a + - const: himax,hx8369 + + reg: + maxItems: 1 + + dc-gpios: + maxItems: 1 + description: D/C pin + + rotation: + enum: [0, 90, 180, 270] + + backlight: + description: + phandle of the backlight device attached to the panel + + im-gpios: + maxItems: 3 + + reset-gpios: + maxItems: 1 + + spi-cpha: true + + spi-cpol: true + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "adafruit,yx350hv15", "himax,hx8357"; + reg = <0>; + spi-max-frequency = <32000000>; + dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + rotation = <90>; + backlight = <&backlight>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/himax,hx8357d.txt b/Documentation/devicetree/bindings/display/himax,hx8357d.txt deleted file mode 100644 index e641f664763d..000000000000 --- a/Documentation/devicetree/bindings/display/himax,hx8357d.txt +++ /dev/null @@ -1,26 +0,0 @@ -Himax HX8357D display panels - -This binding is for display panels using a Himax HX8357D controller in SPI -mode, such as the Adafruit 3.5" TFT for Raspberry Pi. - -Required properties: -- compatible: "adafruit,yx350hv15", "himax,hx8357d" -- dc-gpios: D/C pin -- reg: address of the panel on the SPI bus - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - display@0{ - compatible = "adafruit,yx350hv15", "himax,hx8357d"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - rotation = <90>; - backlight = <&backlight>; - }; diff --git a/MAINTAINERS b/MAINTAINERS index a38c18142bd6..580b5ab614f6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7532,7 +7532,7 @@ F: drivers/gpu/drm/panel/panel-himax-hx8394.c DRM DRIVER FOR HX8357D PANELS S: Orphan T: git https://gitlab.freedesktop.org/drm/misc/kernel.git -F: Documentation/devicetree/bindings/display/himax,hx8357d.txt +F: Documentation/devicetree/bindings/display/himax,hx8357.yaml F: drivers/gpu/drm/tiny/hx8357d.c DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE From 4fb2210866f7bdace7eadf3a275a72cea2a55f7f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 8 Jun 2025 18:21:09 +0200 Subject: [PATCH 06/31] dt-bindings: trivial-devices: Add Analog Devices ADT7411 Describe this SPI-/I2C-Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC. The driver is in hwmon for ages. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20250608162240.3023-2-wsa+renesas@sang-engineering.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 27930708ccd5..cd911c9a209f 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -41,6 +41,8 @@ properties: - adi,ad5110 # Analog Devices ADP5589 Keypad Decoder and I/O Expansion - adi,adp5589 + # Analog Devices ADT7411 Temperature Sensor and 8-channel ADC + - adi,adt7411 # Analog Devices LT7182S Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher - adi,lt7182s # AMS iAQ-Core VOC Sensor From 1b22afb15d697f134bc870a04fb5c7c339b013ce Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 23 Jun 2025 16:40:46 -0400 Subject: [PATCH 07/31] dt-bindings: trivial-devices: add compatible string nxp,isp1301 from isp1301.txt Delete isp1301.txt and add compatible string nxp,isp1301 to trivial-devices because this i2c device have only reg propepty. Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250623204048.2493819-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/trivial-devices.yaml | 2 ++ .../devicetree/bindings/usb/isp1301.txt | 24 ------------------- 2 files changed, 2 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/isp1301.txt diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index cd911c9a209f..db0295bf9fde 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -311,6 +311,8 @@ properties: - national,lm92 # Nuvoton Temperature Sensor - nuvoton,w83773g + # NXP ISP1301 USB transceiver + - nxp,isp1301 # OKI ML86V7667 video decoder - oki,ml86v7667 # ON Semiconductor ADT7462 Temperature, Voltage Monitor and Fan Controller diff --git a/Documentation/devicetree/bindings/usb/isp1301.txt b/Documentation/devicetree/bindings/usb/isp1301.txt deleted file mode 100644 index ecd607dacba5..000000000000 --- a/Documentation/devicetree/bindings/usb/isp1301.txt +++ /dev/null @@ -1,24 +0,0 @@ -* NXP ISP1301 USB transceiver - -Required properties: -- compatible: must be "nxp,isp1301" -- reg: I2C address of the ISP1301 device - -Optional properties of devices using ISP1301: -- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the - ISP1301 instance associated with the respective USB driver - -Example: - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - - usbd@31020000 { - compatible = "nxp,lpc3220-udc"; - reg = <0x31020000 0x300>; - interrupt-parent = <&mic>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - transceiver = <&isp1301>; - }; From de13141516add30adf581561755f3f45d82b50ba Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 24 Jun 2025 18:46:30 -0400 Subject: [PATCH 08/31] dt-bindings: interrupt-controller: Add arm,armv7m-nvic and fix #interrupt-cells According to existed dts arch/arm/boot/dts/armv7-m.dtsi and driver drivers/irqchip/irq-nvic.c, compatible string should be arm,armv7m-nvic, Fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dtb: /interrupt-controller@e000e100: failed to match any schema with compatible: ['arm,armv7m-nvic'] Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250624224630.2518776-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/interrupt-controller/arm,nvic.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml index d89eca956c5f..32dfa2bf05d8 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - arm,armv7m-nvic # deprecated - arm,v6m-nvic - arm,v7m-nvic - arm,v8m-nvic @@ -30,7 +31,7 @@ properties: interrupt-controller: true '#interrupt-cells': - const: 2 + enum: [1, 2] description: | Number of cells to encode an interrupt source: first = interrupt number, second = priority. From 98f79c729d8c862a04089382a5274f084e576d55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Wed, 11 Jun 2025 11:42:09 +0200 Subject: [PATCH 09/31] dt-bindings: interrupt-controller: Convert fsl,mpic-msi to YAML MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As part of a larger effort to bring various PowerPC-related bindings into the YAML world, this patch converts msi-pic.txt to YAML and moves it into the bindings/interrupt-controller/ directory. The conversion may necessarily be a bit hard to read because the binding is quite verbose. Signed-off-by: J. Neuschäfer Link: https://lore.kernel.org/r/20250611-msipic-yaml-v2-1-f2e174c48802@posteo.net Signed-off-by: Rob Herring (Arm) --- .../interrupt-controller/fsl,mpic-msi.yaml | 161 ++++++++++++++++++ .../bindings/powerpc/fsl/msi-pic.txt | 111 ------------ 2 files changed, 161 insertions(+), 111 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml new file mode 100644 index 000000000000..78d784973661 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MSI interrupt controller + +description: | + The Freescale hypervisor and msi-address-64 + ------------------------------------------- + + Normally, PCI devices have access to all of CCSR via an ATMU mapping. The + Freescale MSI driver calculates the address of MSIIR (in the MSI register + block) and sets that address as the MSI message address. + + In a virtualized environment, the hypervisor may need to create an IOMMU + mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement + because of hardware limitations of the Peripheral Access Management Unit + (PAMU), which is currently the only IOMMU that the hypervisor supports. + The ATMU is programmed with the guest physical address, and the PAMU + intercepts transactions and reroutes them to the true physical address. + + In the PAMU, each PCI controller is given only one primary window. The + PAMU restricts DMA operations so that they can only occur within a window. + Because PCI devices must be able to DMA to memory, the primary window must + be used to cover all of the guest's memory space. + + PAMU primary windows can be divided into 256 subwindows, and each + subwindow can have its own address mapping ("guest physical" to "true + physical"). However, each subwindow has to have the same alignment, which + means they cannot be located at just any address. Because of these + restrictions, it is usually impossible to create a 4KB subwindow that + covers MSIIR where it's normally located. + + Therefore, the hypervisor has to create a subwindow inside the same + primary window used for memory, but mapped to the MSIR block (where MSIIR + lives). The first subwindow after the end of guest memory is used for + this. The address specified in the msi-address-64 property is the PCI + address of MSIIR. The hypervisor configures the PAMU to map that address to + the true physical address of MSIIR. + +maintainers: + - J. Neuschäfer + +properties: + compatible: + oneOf: + - enum: + - fsl,mpic-msi + - fsl,mpic-msi-v4.3 + - fsl,ipic-msi + - fsl,vmpic-msi + - fsl,vmpic-msi-v4.3 + - items: + - enum: + - fsl,mpc8572-msi + - fsl,mpc8610-msi + - fsl,mpc8641-msi + - const: fsl,mpic-msi + + reg: + minItems: 1 + items: + - description: Address and length of the shared message interrupt + register set + - description: Address of aliased MSIIR or MSIIR1 register for platforms + that have such an alias. If using MSIIR1, the second region must be + added because different MSI group has different MSIIR1 offset. + + interrupts: + minItems: 1 + maxItems: 16 + description: + Each one of the interrupts here is one entry per 32 MSIs, and routed to + the host interrupt controller. The interrupts should be set as edge + sensitive. If msi-available-ranges is present, only the interrupts that + correspond to available ranges shall be present. + + msi-available-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: First MSI interrupt in this range + - description: Number of MSI interrupts in this range + description: + Define which MSI interrupt can be used in the 256 MSI interrupts. + If not specified, all the MSI interrupts can be used. + Each available range must begin and end on a multiple of 32 (i.e. no + splitting an individual MSI register or the associated PIC interrupt). + + msi-address-64: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + 64-bit PCI address of the MSIIR register. The MSIIR register is used for + MSI messaging. The address of MSIIR in PCI address space is the MSI + message address. + + This property may be used in virtualized environments where the hypervisor + has created an alternate mapping for the MSIR block. See the top-level + description for an explanation. + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,mpic-msi-v4.3 + - fsl,vmpic-msi-v4.3 + then: + properties: + interrupts: + minItems: 16 + description: + Version 4.3 implies that there are 16 shared interrupts, and they + are configured through MSIIR1. + + # MPIC v4.3 does not support this property because the 32 interrupts of + # an individual register are not continuous when using MSIIR1. + msi-available-ranges: false + + reg: + minItems: 2 + + else: + properties: + interrupts: + maxItems: 8 + description: + In versions before 4.3, only 8 shared interrupts are available, and + they are configured through MSIIR. + +unevaluatedProperties: false + +examples: + - | + msi@41600 { + compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = <0xe0 0>, <0xe1 0>, <0xe2 0>, <0xe3 0>, + <0xe4 0>, <0xe5 0>, <0xe6 0>, <0xe7 0>; + }; + + - | + msi@41600 { + compatible = "fsl,mpic-msi-v4.3"; + reg = <0x41600 0x200>, <0x44148 4>; + interrupts = <0xe0 0 0 0>, <0xe1 0 0 0>, <0xe2 0 0 0>, <0xe3 0 0 0>, + <0xe4 0 0 0>, <0xe5 0 0 0>, <0xe6 0 0 0>, <0xe7 0 0 0>, + <0x100 0 0 0>, <0x101 0 0 0>, <0x102 0 0 0>, <0x103 0 0 0>, + <0x104 0 0 0>, <0x105 0 0 0>, <0x106 0 0 0>, <0x107 0 0 0>; + }; + +... diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt deleted file mode 100644 index f8d2b7fe06d6..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt +++ /dev/null @@ -1,111 +0,0 @@ -* Freescale MSI interrupt controller - -Required properties: -- compatible : compatible list, may contain one or two entries - The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, - etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or - "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic - version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is - provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" - should be used. The first entry is optional; the second entry is - required. - -- reg : It may contain one or two regions. The first region should contain - the address and the length of the shared message interrupt register set. - The second region should contain the address of aliased MSIIR or MSIIR1 - register for platforms that have such an alias, if using MSIIR1, the second - region must be added because different MSI group has different MSIIR1 offset. - -- interrupts : each one of the interrupts here is one entry per 32 MSIs, - and routed to the host interrupt controller. the interrupts should - be set as edge sensitive. If msi-available-ranges is present, only - the interrupts that correspond to available ranges shall be present. - -Optional properties: -- msi-available-ranges: use style section to define which - msi interrupt can be used in the 256 msi interrupts. This property is - optional, without this, all the MSI interrupts can be used. - Each available range must begin and end on a multiple of 32 (i.e. - no splitting an individual MSI register or the associated PIC interrupt). - MPIC v4.3 does not support this property because the 32 interrupts of an - individual register are not continuous when using MSIIR1. - -- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register - is used for MSI messaging. The address of MSIIR in PCI address space is - the MSI message address. - - This property may be used in virtualized environments where the hypervisor - has created an alternate mapping for the MSIR block. See below for an - explanation. - - -Example: - msi@41600 { - compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; - reg = <0x41600 0x80>; - msi-available-ranges = <0 0x100>; - interrupts = < - 0xe0 0 - 0xe1 0 - 0xe2 0 - 0xe3 0 - 0xe4 0 - 0xe5 0 - 0xe6 0 - 0xe7 0>; - interrupt-parent = <&mpic>; - }; - - msi@41600 { - compatible = "fsl,mpic-msi-v4.3"; - reg = <0x41600 0x200 0x44148 4>; - interrupts = < - 0xe0 0 0 0 - 0xe1 0 0 0 - 0xe2 0 0 0 - 0xe3 0 0 0 - 0xe4 0 0 0 - 0xe5 0 0 0 - 0xe6 0 0 0 - 0xe7 0 0 0 - 0x100 0 0 0 - 0x101 0 0 0 - 0x102 0 0 0 - 0x103 0 0 0 - 0x104 0 0 0 - 0x105 0 0 0 - 0x106 0 0 0 - 0x107 0 0 0>; - }; - -The Freescale hypervisor and msi-address-64 -------------------------------------------- -Normally, PCI devices have access to all of CCSR via an ATMU mapping. The -Freescale MSI driver calculates the address of MSIIR (in the MSI register -block) and sets that address as the MSI message address. - -In a virtualized environment, the hypervisor may need to create an IOMMU -mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement -because of hardware limitations of the Peripheral Access Management Unit -(PAMU), which is currently the only IOMMU that the hypervisor supports. -The ATMU is programmed with the guest physical address, and the PAMU -intercepts transactions and reroutes them to the true physical address. - -In the PAMU, each PCI controller is given only one primary window. The -PAMU restricts DMA operations so that they can only occur within a window. -Because PCI devices must be able to DMA to memory, the primary window must -be used to cover all of the guest's memory space. - -PAMU primary windows can be divided into 256 subwindows, and each -subwindow can have its own address mapping ("guest physical" to "true -physical"). However, each subwindow has to have the same alignment, which -means they cannot be located at just any address. Because of these -restrictions, it is usually impossible to create a 4KB subwindow that -covers MSIIR where it's normally located. - -Therefore, the hypervisor has to create a subwindow inside the same -primary window used for memory, but mapped to the MSIR block (where MSIIR -lives). The first subwindow after the end of guest memory is used for -this. The address specified in the msi-address-64 property is the PCI -address of MSIIR. The hypervisor configures the PAMU to map that address to -the true physical address of MSIIR. From fd8fca21629d8e1a68e7900ad804946e3b66eddb Mon Sep 17 00:00:00 2001 From: Meng Li Date: Sun, 8 Jun 2025 11:06:15 +0800 Subject: [PATCH 10/31] dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1046a-wdt Add compatible string fsl,ls1046a-wdt for ls1046a SoC. fsl,ls1046a-wdt allows big-endian property. Signed-off-by: Meng Li Reviewed-by: Rob Herring (Arm) Reviewed-by: Ahmad Fatoum Reviewed-by: Frank Li Link: https://lore.kernel.org/r/20250608030616.3874517-2-Meng.Li@windriver.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index 8a6c3a75a547..34951783a633 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -37,6 +37,7 @@ properties: - fsl,ls1012a-wdt - fsl,ls1021a-wdt - fsl,ls1043a-wdt + - fsl,ls1046a-wdt - fsl,vf610-wdt - const: fsl,imx21-wdt @@ -105,6 +106,7 @@ allOf: - fsl,ls1012a-wdt - fsl,ls1021a-wdt - fsl,ls1043a-wdt + - fsl,ls1046a-wdt then: properties: big-endian: false From 49ed6868c10e2a11bb44ea836ecf88ca4122f303 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Jul 2025 11:50:20 +0200 Subject: [PATCH 11/31] docs: dt: writing-bindings: Rephrase typical fallback (superset) usage When speaking about compatibles for new devices comparing to "prior implementations", usually we expect new device to come with more features, thus logically it is a superset, not subset, of "prior implementations". Suggested-by: Conor Dooley Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250707095019.66792-4-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-bindings.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index 1ad081de2dd0..66c94b5adc87 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -40,9 +40,9 @@ Properties ========== - DO make 'compatible' properties specific. DON'T use wildcards in compatible - strings. DO use fallback compatibles when devices are the same as or a subset - of prior implementations. DO add new compatibles in case there are new - features or bugs. + strings. DO use fallback compatibles when devices are the same as or a + superset of prior implementations. DO add new compatibles in case there are + new features or bugs. - DO use a vendor prefix on device-specific property names. Consider if properties could be common among devices of the same class. Check other From b57ce9630bab1a468643fd5fb34d42cb936f0cb0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Jul 2025 11:50:21 +0200 Subject: [PATCH 12/31] docs: dt: writing-bindings: Express better expectations of "specific" Devicetree bindings are supposed to be specific in terms of compatibles and other properties. Short "specific" has many implications, so extend the description to cover them: 1. Mention no family names and avoid generic SoC fallbacks in compatible. The list grew, mixing DO's and DON'T's, so split it into multiple items. 2. No properties implied by the compatible. 3. Document desired lack of ABI impact and acceptable solution if such needs arises: clearly marking it in commit msg. All above follows established Devicetree bindings maintainers review practice, so no new rules in practice are introduced here. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250707095019.66792-5-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/writing-bindings.rst | 27 +++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index 66c94b5adc87..962e38a1751a 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -39,10 +39,18 @@ Overall design Properties ========== -- DO make 'compatible' properties specific. DON'T use wildcards in compatible - strings. DO use fallback compatibles when devices are the same as or a - superset of prior implementations. DO add new compatibles in case there are - new features or bugs. +- DO make 'compatible' properties specific. + + - DON'T use wildcards or device-family names in compatible strings. + + - DO use fallback compatibles when devices are the same as or a superset of + prior implementations. + + - DO add new compatibles in case there are new features or bugs. + + - DO use a SoC-specific compatible for all SoC devices, followed by a + fallback if appropriate. SoC-specific compatibles are also preferred for + the fallbacks. - DO use a vendor prefix on device-specific property names. Consider if properties could be common among devices of the same class. Check other @@ -51,12 +59,21 @@ Properties - DON'T redefine common properties. Just reference the definition and define constraints specific to the device. +- DON'T add properties to avoid a specific compatible. DON'T add properties if + they are implied by (deducible from) the compatible. + - DO use common property unit suffixes for properties with scientific units. Recommended suffixes are listed at https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/property-units.yaml - DO define properties in terms of constraints. How many entries? What are - possible values? What is the order? + possible values? What is the order? All these constraints represent the ABI + as well. + +- DON'T make changes that break the ABI without explicit and detailed rationale + for why the changes have to be made and their impact. ABI impact goes beyond + the Linux kernel, because it also covers other open-source upstream projects. + Typical cases and caveats ========================= From 62c51c2b38724e80654af04e1ee09e99eece5925 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Jul 2025 11:50:22 +0200 Subject: [PATCH 13/31] docs: dt: writing-bindings: Consistently use single-whitespace Document uses only single whitespace after full stop, so fix inconsistency. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250707095019.66792-6-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-bindings.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index 962e38a1751a..a2d2afd099c0 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -81,7 +81,7 @@ Typical cases and caveats - Phandle entries, like clocks/dmas/interrupts/resets, should always be explicitly ordered. Include the {clock,dma,interrupt,reset}-names if there is more than one phandle. When used, both of these fields need the same - constraints (e.g. list of items). + constraints (e.g. list of items). - For names used in {clock,dma,interrupt,reset}-names, do not add any suffix, e.g.: "tx" instead of "txirq" (for interrupt). From 26ff041e2a13cefe74b4533fd7bbff3114521422 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Mon, 12 May 2025 15:43:32 +0200 Subject: [PATCH 14/31] MAINTAINERS: adjust file entry in INTEL STRATIX10 FIRMWARE DRIVERS Commit fbfb64987062 ("dt-bindings: firmware: stratix10: Convert to json-schema") renames intel,stratix10-svc.txt to intel,stratix10-svc.yaml in Documentation/devicetree/bindings/firmware/ as part of this dt-binding conversion, but misses to adjust the file entry in INTEL STRATIX10 FIRMWARE DRIVERS. Adjust the file entry after the conversion. Signed-off-by: Lukas Bulwahn Acked-by: Dinh Nguyen Link: https://lore.kernel.org/r/20250512134332.36366-1-lukas.bulwahn@redhat.com Signed-off-by: Rob Herring (Arm) --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 580b5ab614f6..402da86200c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12463,7 +12463,7 @@ L: linux-kernel@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu -F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml F: drivers/firmware/stratix10-rsu.c F: drivers/firmware/stratix10-svc.c F: include/linux/firmware/intel/stratix10-smc.h From 651fcd25527cd2ac0116530ca53c637d02562bca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 13 Jul 2025 14:46:36 +0200 Subject: [PATCH 15/31] docs: dt: submitting-patches: Avoid 'YAML' in the subject and add an example Patches adding new device bindings should avoid 'YAML' keyword in the subject, because all bindings are supposed to be in DT schema format, which uses YAML. The DT schema is welcomed only in case of patches doing conversion. Effectively people get confused that subject should not contain anything else than device name after the prefix, so add two recommended examples. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250713-dt-bindings-docs-v2-1-672c898054ae@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/submitting-patches.rst | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index f3e23e69a638..46d0b036c97e 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -21,8 +21,16 @@ I. For patch submitters ": dt-bindings: ..." The 80 characters of the subject are precious. It is recommended to not - use "Documentation" or "doc" because that is implied. All bindings are - docs. Repeating "binding" again should also be avoided. + use "Documentation", "doc" or "YAML" because that is implied. All + bindings are docs and all new bindings are supposed to be in Devicetree + schema format. Repeating "binding" again should also be avoided, so for + a new device it is often enough for example:: + + "dt-bindings: iio: adc: Add ROHM BD79100G" + + Conversion of other formats to DT schema:: + + "dt-bindings: iio: adc: adi,ad7476: Convert to DT schema" 2) DT binding files are written in DT schema format using json-schema vocabulary and YAML file format. The DT binding files must pass validation From a1d87a3586152f52856b449c4787f21cb35d430f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 13 Jul 2025 14:46:37 +0200 Subject: [PATCH 16/31] docs: dt: writing-bindings: Document compatible and filename naming Document established Devicetree bindings maintainers review practices: 1. Compatibles should not use bus suffixes to encode the type of interface, because the parent bus node defines that interface, e.g. "vendor,device" instead of "vendor,device-i2c" + "vendor,device-spi". 2. If the compatible represents the device as a whole, it should not contain the type of device in the name. 3. Filenames should match compatible. The best if match is 100%, but if binding has multiple compatibles, then one of the fallbacks should be used. Alternatively a genericish name is allowed if it follows "vendor,device" style. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250713-dt-bindings-docs-v2-2-672c898054ae@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-bindings.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index a2d2afd099c0..e63de88385b5 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -52,6 +52,10 @@ Properties fallback if appropriate. SoC-specific compatibles are also preferred for the fallbacks. + - DON'T use bus suffixes to encode the type of interface device is using. + The parent bus node already implies that interface. DON'T add the type of + device, if the device cannot be anything else. + - DO use a vendor prefix on device-specific property names. Consider if properties could be common among devices of the same class. Check other existing bindings for similar devices. @@ -101,6 +105,10 @@ Typical cases and caveats - "syscon" is not a generic property. Use vendor and type, e.g. "vendor,power-manager-syscon". +- Bindings files should be named like compatible: vendor,device.yaml. In case + of multiple compatibles in the binding, use one of the fallbacks or a more + generic name, yet still matching compatible style. + Board/SoC .dts Files ==================== From 6a57cf210711c068a650bd86acae4a88303dfd5d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 13 Jul 2025 14:46:38 +0200 Subject: [PATCH 17/31] docs: dt: writing-bindings: Document discouraged instance IDs Document established Devicetree bindings maintainers review practice: instance indexes, either as properties or as custom new OF alias, are not accepted. Recommended way is to use, depending on the situation/hardware: different compatible, cell arguments or syscon phandle arguments. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250713-dt-bindings-docs-v2-3-672c898054ae@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-bindings.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index e63de88385b5..f8e0293a7c06 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -105,6 +105,11 @@ Typical cases and caveats - "syscon" is not a generic property. Use vendor and type, e.g. "vendor,power-manager-syscon". +- Do not add instance index (IDs) properties or custom OF aliases. If the + devices have different programming model, they might need different + compatibles. If such devices use some other device in a different way, e.g. + they program the phy differently, use cell/phandle arguments. + - Bindings files should be named like compatible: vendor,device.yaml. In case of multiple compatibles in the binding, use one of the fallbacks or a more generic name, yet still matching compatible style. From 3f0a014f3b6b5a953a6d13d358a39154d5cdf688 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 13 Jul 2025 14:46:39 +0200 Subject: [PATCH 18/31] docs: dt: writing-schema: Document preferred order of properties Document established Devicetree bindings maintainers review practice: using DTS coding style property order in both 'properties' and 'required' secions. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250713-dt-bindings-docs-v2-4-672c898054ae@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-schema.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index fc73072f12fc..470d1521fa17 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -171,6 +171,9 @@ Coding style Use YAML coding style (two-space indentation). For DTS examples in the schema, preferred is four-space indentation. +Place entries in 'properties' and 'required' sections in the same order, using +style from Documentation/devicetree/bindings/dts-coding-style.rst. + Testing ------- From 7bce7ae1a1f6cfbc81ed60ddf65b306bb1ebf8f2 Mon Sep 17 00:00:00 2001 From: Mikhail Kalashnikov Date: Fri, 11 Jul 2025 11:57:27 +0800 Subject: [PATCH 19/31] dt-bindings: gpu: mali-bifrost: Add Allwinner A523 compatible Add a compatible for the Allwinner A523 SoC, with an integrated ARM Mali G57 MC1 (Valhall-JM) GPU. Signed-off-by: Mikhail Kalashnikov Link: https://lore.kernel.org/r/20250711035730.17507-2-iuncuim@gmail.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index b8d659d272d0..aa19f8819231 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -40,6 +40,7 @@ properties: - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable - items: - enum: + - allwinner,sun55i-a523-mali - mediatek,mt8188-mali - mediatek,mt8192-mali - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable From 3f66b5b401b58c38f613563e7d01719dfa6b9e52 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Jul 2025 13:07:55 -0500 Subject: [PATCH 20/31] dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema Convert the Applied Micro X-Gene MSI controller binding to DT schema format. MSI controllers go in interrupt-controller directory so move the schema there. Link: https://lore.kernel.org/r/20250710180757.2970583-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../interrupt-controller/apm,xgene1-msi.yaml | 54 +++++++++++++++ .../devicetree/bindings/pci/xgene-pci-msi.txt | 68 ------------------- MAINTAINERS | 2 +- 3 files changed, 55 insertions(+), 69 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml delete mode 100644 Documentation/devicetree/bindings/pci/xgene-pci-msi.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml new file mode 100644 index 000000000000..49db952697f3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/apm,xgene1-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AppliedMicro X-Gene v1 PCIe MSI controller + +maintainers: + - Toan Le + +properties: + compatible: + const: apm,xgene1-msi + + msi-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 16 + +required: + - compatible + - msi-controller + - reg + - interrupts + +additionalProperties: false + +examples: + - | + msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x79000000 0x900000>; + interrupts = <0x0 0x10 0x4>, + <0x0 0x11 0x4>, + <0x0 0x12 0x4>, + <0x0 0x13 0x4>, + <0x0 0x14 0x4>, + <0x0 0x15 0x4>, + <0x0 0x16 0x4>, + <0x0 0x17 0x4>, + <0x0 0x18 0x4>, + <0x0 0x19 0x4>, + <0x0 0x1a 0x4>, + <0x0 0x1b 0x4>, + <0x0 0x1c 0x4>, + <0x0 0x1d 0x4>, + <0x0 0x1e 0x4>, + <0x0 0x1f 0x4>; + }; diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt deleted file mode 100644 index 85d9b95234f7..000000000000 --- a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt +++ /dev/null @@ -1,68 +0,0 @@ -* AppliedMicro X-Gene v1 PCIe MSI controller - -Required properties: - -- compatible: should be "apm,xgene1-msi" to identify - X-Gene v1 PCIe MSI controller block. -- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node -- reg: physical base address (0x79000000) and length (0x900000) for controller - registers. These registers include the MSI termination address and data - registers as well as the MSI interrupt status registers. -- reg-names: not required -- interrupts: A list of 16 interrupt outputs of the controller, starting from - interrupt number 0x10 to 0x1f. -- interrupt-names: not required - -Each PCIe node needs to have property msi-parent that points to an MSI -controller node - -Examples: - -SoC DTSI: - - + MSI node: - msi@79000000 { - compatible = "apm,xgene1-msi"; - msi-controller; - reg = <0x00 0x79000000 0x0 0x900000>; - interrupts = <0x0 0x10 0x4> - <0x0 0x11 0x4> - <0x0 0x12 0x4> - <0x0 0x13 0x4> - <0x0 0x14 0x4> - <0x0 0x15 0x4> - <0x0 0x16 0x4> - <0x0 0x17 0x4> - <0x0 0x18 0x4> - <0x0 0x19 0x4> - <0x0 0x1a 0x4> - <0x0 0x1b 0x4> - <0x0 0x1c 0x4> - <0x0 0x1d 0x4> - <0x0 0x1e 0x4> - <0x0 0x1f 0x4>; - }; - - + PCIe controller node with msi-parent property pointing to MSI node: - pcie0: pcie@1f2b0000 { - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; - dma-coherent; - clocks = <&pcie0clk 0>; - msi-parent= <&msi>; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 402da86200c5..a0d5bc02c7fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19146,7 +19146,7 @@ M: Toan Le L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt +F: Documentation/devicetree/bindings/interrupt-controller/apm,xgene1-msi.yaml F: drivers/pci/controller/pci-xgene-msi.c PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS From 828e50188de5fe898293dfb6e151f88b3d942407 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 1 Jul 2025 16:00:45 -0500 Subject: [PATCH 21/31] dt-bindings: trivial-devices: Add undocumented hwmon devices There's a bunch of undocumented, but already in use trivial hwmon devices. Most are just variants of existing trivial devices. Acked-by: Guenter Roeck Link: https://lore.kernel.org/r/20250701-dt-hwmon-compatibles-v1-6-ad99e65cf11b@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/trivial-devices.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index db0295bf9fde..95c9bd36cc63 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -39,10 +39,16 @@ properties: - ad,adm9240 # AD5110 - Nonvolatile Digital Potentiometer - adi,ad5110 + # Temperature sensor with integrated fan control + - adi,adm1027 # Analog Devices ADP5589 Keypad Decoder and I/O Expansion - adi,adp5589 # Analog Devices ADT7411 Temperature Sensor and 8-channel ADC - adi,adt7411 + # Temperature sensor with integrated fan control + - adi,adt7463 + # Temperature sensor with integrated fan control + - adi,adt7468 # Analog Devices LT7182S Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher - adi,lt7182s # AMS iAQ-Core VOC Sensor @@ -293,6 +299,8 @@ properties: - mps,mp2891 # Monolithic Power Systems Inc. multi-phase controller mp2993 - mps,mp2993 + # Monolithic Power Systems Inc. hot-swap protection device + - mps,mp5023 # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5920 - mps,mp5920 # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 @@ -301,12 +309,24 @@ properties: - mps,mp9941 # Temperature sensor with integrated fan control - national,lm63 + # Temperature sensor with integrated fan control + - national,lm64 + # Temperature sensor + - national,lm95235 + # Temperature sensor + - national,lm95245 + # Temperature sensor with integrated fan control + - national,lm96163 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor - national,lm80 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor - national,lm81 # Temperature sensor with integrated fan control - national,lm85 + # Temperature sensor with integrated fan control + - national,lm85b + # Temperature sensor with integrated fan control + - national,lm85c # I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator - national,lm92 # Nuvoton Temperature Sensor @@ -361,12 +381,38 @@ properties: - silabs,si7020 # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply - skyworks,sky81452 + # Temperature sensor with integrated fan control + - smsc,emc6d100 + # Temperature sensor with integrated fan control + - smsc,emc6d101 + # Temperature sensor with integrated fan control + - smsc,emc6d102 + # Temperature sensor with integrated fan control + - smsc,emc6d103 + # Temperature sensor with integrated fan control + - smsc,emc6d103s # SparkFun Qwiic Joystick (COM-15168) with i2c interface - sparkfun,qwiic-joystick # Sierra Wireless mangOH Green SPI IoT interface - swir,mangoh-iotport-spi # Ambient Light Sensor with SMBUS/Two Wire Serial Interface - taos,tsl2550 + # Digital PWM System Controller PMBus + - ti,cd9200 + # Digital PWM System Controller PMBus + - ti,cd9220 + # Digital PWM System Controller PMBus + - ti,cd9222 + # Digital PWM System Controller PMBus + - ti,cd9224 + # Digital PWM System Controller PMBus + - ti,cd9240 + # Digital PWM System Controller PMBus + - ti,cd9244 + # Digital PWM System Controller PMBus + - ti,cd9246 + # Digital PWM System Controller PMBus + - ti,cd9248 # Temperature and humidity sensor with i2c interface - ti,hdc1000 # Temperature and humidity sensor with i2c interface @@ -394,6 +440,10 @@ properties: - ti,tmp125 # TI DC-DC converter on PMBus - ti,tps40400 + # TI DCAP+ multiphase controller + - ti,tps53647 + # TI DCAP+ multiphase controller + - ti,tps53667 # TI Dual channel DCAP+ multiphase controller TPS53676 with AVSBus - ti,tps53676 # TI Dual channel DCAP+ multiphase controller TPS53679 From 2382aedd17d7bd8f4cbf0c50f9298851c00ebf86 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 2 Jul 2025 17:26:24 -0500 Subject: [PATCH 22/31] dt-bindings: net: Convert Marvell Armada NETA and BM to DT schema Convert Marvell Armada NETA Ethernet Controller and Buffer Manager bindings to schema. It is a straight forward conversion. Link: https://lore.kernel.org/r/20250702222626.2761199-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/net/marvell,armada-370-neta.yaml | 79 +++++++++++++++++++ .../net/marvell,armada-380-neta-bm.yaml | 60 ++++++++++++++ .../bindings/net/marvell-armada-370-neta.txt | 50 ------------ .../bindings/net/marvell-neta-bm.txt | 47 ----------- .../devicetree/bindings/vendor-prefixes.yaml | 1 + 5 files changed, 140 insertions(+), 97 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml create mode 100644 Documentation/devicetree/bindings/net/marvell,armada-380-neta-bm.yaml delete mode 100644 Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt delete mode 100644 Documentation/devicetree/bindings/net/marvell-neta-bm.txt diff --git a/Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml b/Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml new file mode 100644 index 000000000000..8814977da024 --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/marvell,armada-370-neta.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370/XP/3700/AC5 Ethernet Controller (NETA) + +maintainers: + - Marcin Wojtas + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + +properties: + compatible: + enum: + - marvell,armada-370-neta + - marvell,armada-xp-neta + - marvell,armada-3700-neta + - marvell,armada-ac5-neta + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: bus + + phys: + maxItems: 1 + + tx-csum-limit: + description: Maximum MTU in bytes for Tx checksum offload; default is 1600 for + armada-370-neta and 9800 for others. + $ref: /schemas/types.yaml#/definitions/uint32 + + buffer-manager: + description: Phandle to hardware buffer manager. + $ref: /schemas/types.yaml#/definitions/phandle + + bm,pool-long: + description: Pool ID for packets larger than the short threshold. + $ref: /schemas/types.yaml#/definitions/uint32 + + bm,pool-short: + description: Pool ID for packets smaller than the long threshold. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x2500>; + interrupts = <8>; + clocks = <&gate_clk 4>; + tx-csum-limit = <9800>; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; + }; diff --git a/Documentation/devicetree/bindings/net/marvell,armada-380-neta-bm.yaml b/Documentation/devicetree/bindings/net/marvell,armada-380-neta-bm.yaml new file mode 100644 index 000000000000..9392e7126e3e --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell,armada-380-neta-bm.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/marvell,armada-380-neta-bm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 380/XP Buffer Manager (BM) + +maintainers: + - Marcin Wojtas + +description: + In order to see how to hook the BM to a given ethernet port, please refer to + Documentation/devicetree/bindings/net/marvell,armada-370-neta.yaml. + +properties: + compatible: + const: marvell,armada-380-neta-bm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + internal-mem: + description: Phandle to internal SRAM region + $ref: /schemas/types.yaml#/definitions/phandle + +patternProperties: + "^pool[0-3],capacity$": + description: + size of external buffer pointers' ring maintained in DRAM for pool 0-3 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 128 + maximum: 16352 + + "^pool[0-3],pkt-size$": + description: + maximum packet size for a short buffer pool entry (pool 0-3) + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - internal-mem + +additionalProperties: false + +examples: + - | + bm@c8000 { + compatible = "marvell,armada-380-neta-bm"; + reg = <0xc8000 0xac>; + clocks = <&gateclk 13>; + internal-mem = <&bm_bppi>; + pool2,capacity = <4096>; + pool1,pkt-size = <512>; + }; diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt deleted file mode 100644 index 2bf31572b08d..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA) - -Required properties: -- compatible: could be one of the following: - "marvell,armada-370-neta" - "marvell,armada-xp-neta" - "marvell,armada-3700-neta" - "marvell,armada-ac5-neta" -- reg: address and length of the register set for the device. -- interrupts: interrupt for the device -- phy: See ethernet.txt file in the same directory. -- phy-mode: See ethernet.txt file in the same directory -- clocks: List of clocks for this device. At least one clock is - mandatory for the core clock. If several clocks are given, then the - clock-names property must be used to identify them. - -Optional properties: -- tx-csum-limit: maximum mtu supported by port that allow TX checksum. - Value is presented in bytes. If not used, by default 1600B is set for - "marvell,armada-370-neta" and 9800B for others. -- clock-names: List of names corresponding to clocks property; shall be - "core" for core clock and "bus" for the optional bus clock. -- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt - -Optional properties (valid only for Armada XP/38x): - -- buffer-manager: a phandle to a buffer manager node. Please refer to - Documentation/devicetree/bindings/net/marvell-neta-bm.txt -- bm,pool-long: ID of a pool, that will accept all packets of a size - higher than 'short' pool's threshold (if set) and up to MTU value. - Obligatory, when the port is supposed to use hardware - buffer management. -- bm,pool-short: ID of a pool, that will be used for accepting - packets of a size lower than given threshold. If not set, the port - will use a single 'long' pool for all packets, as defined above. - -Example: - -ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; - interrupts = <8>; - clocks = <&gate_clk 4>; - tx-csum-limit = <9800> - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-neta-bm.txt b/Documentation/devicetree/bindings/net/marvell-neta-bm.txt deleted file mode 100644 index 07b31050dbe5..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-neta-bm.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Marvell Armada 380/XP Buffer Manager driver (BM) - -Required properties: - -- compatible: should be "marvell,armada-380-neta-bm". -- reg: address and length of the register set for the device. -- clocks: a pointer to the reference clock for this device. -- internal-mem: a phandle to BM internal SRAM definition. - -Optional properties (port): - -- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained - in DRAM. Can be set for each pool (id 0 : 3) separately. The value has - to be chosen between 128 and 16352 and it also has to be aligned to 32. - Otherwise the driver would adjust a given number or choose default if - not set. -- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer - pointers' pool (id 0 : 3). It will be taken into consideration only when pool - type is 'short'. For 'long' ones it would be overridden by port's MTU. - If not set a driver will choose a default value. - -In order to see how to hook the BM to a given ethernet port, please -refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt. - -Example: - -- main node: - -bm: bm@c8000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc8000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - pool2,capacity = <4096>; - pool1,pkt-size = <512>; -}; - -- internal SRAM node: - -bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; -}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5d2a7a8d3ac6..741b545e3ab0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -21,6 +21,7 @@ patternProperties: "^(pciclass|pinctrl-single|#pinctrl-single|PowerPC),.*": true "^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true + "^pool[0-3],.*": true # Keep list in alphabetical order. "^100ask,.*": From b06d6a1d0cc6d0d44a8175108356016057718081 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 21 May 2025 17:00:09 +0400 Subject: [PATCH 23/31] dt-bindings: timer: via,vt8500-timer: Convert to YAML Rewrite the textual description for the VIA/WonderMedia timer as YAML schema. The IP can generate up to four interrupts from four respective match registers, so reflect that in the schema. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20250521-vt8500-timer-updates-v5-1-7e4bd11df72e@gmail.com Signed-off-by: Rob Herring (Arm) --- .../bindings/timer/via,vt8500-timer.txt | 15 ------ .../bindings/timer/via,vt8500-timer.yaml | 51 +++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 52 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/via,vt8500-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt b/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt deleted file mode 100644 index 901c73f0d8ef..000000000000 --- a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt +++ /dev/null @@ -1,15 +0,0 @@ -VIA/Wondermedia VT8500 Timer ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-timer" -- reg : Should contain 1 register ranges(address and length) -- interrupts : interrupt for the timer - -Example: - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; diff --git a/Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml b/Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml new file mode 100644 index 000000000000..e748149948f3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/via,vt8500-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Timer + +description: + This is the timer block that is a standalone part of the system power + management controller on VIA/WonderMedia SoCs (VIA VT8500 and alike). + The hardware has a single 32-bit counter running at 3 MHz and four match + registers, each of which is associated with a dedicated match interrupt, + and the first of which can also serve as the system watchdog (if the + watchdog function is enabled, it will reset the system upon match instead + of triggering its respective interrupt) + +maintainers: + - Alexey Charkov + +properties: + compatible: + const: via,vt8500-timer + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: Channel 0 match. Note that if the watchdog function + is enabled, this interrupt will not fire and the system will + reboot instead once the counter reaches match register 0 value + - description: Channel 1 match + - description: Channel 2 match + - description: Channel 3 match + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a0d5bc02c7fc..98229b793161 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3508,6 +3508,7 @@ F: Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml F: Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml F: Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml F: Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml +F: Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml F: arch/arm/boot/dts/vt8500/ F: arch/arm/mach-vt8500/ F: drivers/clocksource/timer-vt8500.c From 83e6769f80a1b8e1a97f8d1cecd8631b976fc009 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 16 Jun 2025 14:24:38 -0400 Subject: [PATCH 24/31] dt-bindings: display: imx: convert fsl,dcu.txt to yaml format Convert fsl,dcu.txt to yaml format. Additional changes: - remove label in example. - change node to display-controller in example. - use 32bit address in example. - add interrupts property. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li Reviewed-by: Stefan Agner Link: https://lore.kernel.org/r/20250616182439.1989840-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/fsl,dcu.txt | 34 --------- .../bindings/display/fsl,ls1021a-dcu.yaml | 71 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 72 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/fsl,dcu.txt create mode 100644 Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt deleted file mode 100644 index 63ec2a624aa9..000000000000 --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt +++ /dev/null @@ -1,34 +0,0 @@ -Device Tree bindings for Freescale DCU DRM Driver - -Required properties: -- compatible: Should be one of - * "fsl,ls1021a-dcu". - * "fsl,vf610-dcu". - -- reg: Address and length of the register set for dcu. -- clocks: Handle to "dcu" and "pix" clock (in the order below) - This can be the same clock (e.g. LS1021a) - See ../clocks/clock-bindings.txt for details. -- clock-names: Should be "dcu" and "pix" - See ../clocks/clock-bindings.txt for details. -- big-endian Boolean property, LS1021A DCU registers are big-endian. -- port Video port for the panel output - -Optional properties: -- fsl,tcon: The phandle to the timing controller node. - -Examples: -dcu: dcu@2ce0000 { - compatible = "fsl,ls1021a-dcu"; - reg = <0x0 0x2ce0000 0x0 0x10000>; - clocks = <&platform_clk 0>, <&platform_clk 0>; - clock-names = "dcu", "pix"; - big-endian; - fsl,tcon = <&tcon>; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml b/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml new file mode 100644 index 000000000000..72d14babe993 --- /dev/null +++ b/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale DCU DRM Driver + +maintainers: + - Frank Li + +properties: + compatible: + enum: + - fsl,ls1021a-dcu + - fsl,vf610-dcu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: dcu + - const: pix + + big-endian: true + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for the panel output + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + fsl,tcon: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the timing controller node. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + display-controller@2ce0000 { + compatible = "fsl,ls1021a-dcu"; + reg = <0x2ce0000 0x10000>; + clocks = <&platform_clk 0>, <&platform_clk 0>; + clock-names = "dcu", "pix"; + big-endian; + fsl,tcon = <&tcon>; + + port { + endpoint { + remote-endpoint = <&panel_out>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 98229b793161..1040202b00e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8049,7 +8049,7 @@ M: Alison Wang L: dri-devel@lists.freedesktop.org S: Supported T: git https://gitlab.freedesktop.org/drm/misc/kernel.git -F: Documentation/devicetree/bindings/display/fsl,dcu.txt +F: Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml F: Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml F: drivers/gpu/drm/fsl-dcu/ From 934da599e694d476f493d3927a30414e98a81561 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Jul 2025 14:30:04 +0200 Subject: [PATCH 25/31] dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints 'minItems' alone does not impose upper bound, unlike 'maxItems' which implies lower bound. Add missing clock constraint so the list will have exact number of items (clocks). Fixes: 8cae15c60cf0 ("dt-bindings: display: add Unisoc's dpu bindings") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250720123003.37662-3-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml index 4ebea60b8c5b..8c52fa0ea5f8 100644 --- a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml +++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml @@ -25,7 +25,7 @@ properties: maxItems: 1 clocks: - minItems: 2 + maxItems: 2 clock-names: items: From 2558df8c13ae3bd6c303b28f240ceb0189519c91 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Jul 2025 14:30:05 +0200 Subject: [PATCH 26/31] dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints 'minItems' alone does not impose upper bound, unlike 'maxItems' which implies lower bound. Add missing clock constraint so the list will have exact number of items (clocks). Fixes: 2295bbd35edb ("dt-bindings: display: add Unisoc's mipi dsi controller bindings") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250720123003.37662-4-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml index bc5594d18643..300bf2252c3e 100644 --- a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml +++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml @@ -20,7 +20,7 @@ properties: maxItems: 2 clocks: - minItems: 1 + maxItems: 1 clock-names: items: From 7ce3c2713b45e349468fd5f9166f376ad9a361e3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 24 Jul 2025 12:57:57 +0200 Subject: [PATCH 27/31] dt-bindings: interrupt-controller: Add missing Xilinx INTC binding Add missing description for AMD/Xilinx interrupt controller. The binding is used by Microblaze before dt-binding even existed but never been documented properly. IP acts as primary interrupt controller on Microblaze systems or can be used as secondary interrupt controller on ARM based systems like Zynq, ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on Microblaze-V (Risc-V) systems. Over the years IP exists in multiple variants based on attached bus as OPB, PLB or AXI that's why generic filename is used. Property xlnx,kind-of-intr is in hex because every bit position corresponds to interrupt line. Controller support mixing edge or level interrupts together and this is the property which distinguish them. Signed-off-by: Michal Simek Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/2b9d4a3a693f501d420da88b8418732ba9def877.1753354675.git.michal.simek@amd.com Signed-off-by: Rob Herring (Arm) --- .../interrupt-controller/xlnx,intc.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml new file mode 100644 index 000000000000..b4f58ed25993 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Interrupt Controller + +maintainers: + - Michal Simek + +description: + The controller is a soft IP core that is configured at build time for the + number of interrupts and the type of each interrupt. These details cannot + be changed at run time. + +properties: + compatible: + const: xlnx,xps-intc-1.00.a + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + "#interrupt-cells": + const: 2 + description: + Specifies the number of cells needed to encode an interrupt source. + The value shall be a minimum of 1. The Xilinx device trees typically + use 2 but the 2nd value is not used. + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: + Specifies the interrupt of the parent controller from which it is chained. + + xlnx,kind-of-intr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + A 32 bit value specifying the interrupt type for each possible interrupt + (1 = edge, 0 = level). The interrupt type typically comes in thru + the device tree node of the interrupt generating device, but in this case + the interrupt type is determined by the interrupt controller based on how + it was implemented. + + xlnx,num-intr-inputs: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + description: + Specifies the number of interrupts supported by the specific + implementation of the controller. + +required: + - reg + - "#interrupt-cells" + - interrupt-controller + - xlnx,kind-of-intr + - xlnx,num-intr-inputs + +additionalProperties: false + +examples: + - | + interrupt-controller@41800000 { + compatible = "xlnx,xps-intc-1.00.a"; + reg = <0x41800000 0x10000>; + #interrupt-cells = <2>; + interrupt-controller; + xlnx,kind-of-intr = <0x1>; + xlnx,num-intr-inputs = <1>; + }; From fa8c0b1c7931b76171571a8e25578844caa1c10d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 24 Jul 2025 12:46:23 -0400 Subject: [PATCH 28/31] dt-bindings: interrupt-controller: Add fsl,icoll.yaml Add fsl,icoll.yaml for i.MX23 and i.MX28. Also add a generic fallback compatible string "fsl,icoll" for legacy devices, which have existed for over 15 years. Reviewed-by: Conor Dooley Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250724164624.1271661-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../interrupt-controller/fsl,icoll.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,icoll.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,icoll.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,icoll.yaml new file mode 100644 index 000000000000..7b09fd7d588f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,icoll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,icoll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS icoll Interrupt controller + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx23-icoll + - fsl,imx28-icoll + - const: fsl,icoll + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@80000000 { + compatible = "fsl,imx28-icoll", "fsl,icoll"; + reg = <0x80000000 0x2000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + From 1693d187725d75a9b28a5e4531ca8582b4eb0473 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 24 Jul 2025 15:03:41 -0400 Subject: [PATCH 29/31] dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format Convert fsl,vf610-mscm-ir.txt to yaml format. Additional changes: - remove label at example dts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250724190342.1321632-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../arm/freescale/fsl,vf610-mscm-ir.txt | 30 --------- .../fsl,vf610-mscm-ir.yaml | 63 +++++++++++++++++++ 2 files changed, 63 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt deleted file mode 100644 index 6dd6f399236d..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt +++ /dev/null @@ -1,30 +0,0 @@ -Freescale Vybrid Miscellaneous System Control - Interrupt Router - -The MSCM IP contains multiple sub modules, this binding describes the second -block of registers which control the interrupt router. The interrupt router -allows to configure the recipient of each peripheral interrupt. Furthermore -it controls the directed processor interrupts. The module is available in all -Vybrid SoC's but is only really useful in dual core configurations (VF6xx -which comes with a Cortex-A5/Cortex-M4 combination). - -Required properties: -- compatible: "fsl,vf610-mscm-ir" -- reg: the register range of the MSCM Interrupt Router -- fsl,cpucfg: The handle to the MSCM CPU configuration node, required - to get the current CPU ID -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: Two cells, interrupt number and cells. - The hardware interrupt number according to interrupt - assignment of the interrupt router is required. - Flags get passed only when using GIC as parent. Flags - encoding as documented by the GIC bindings. - -Example: - mscm_ir: interrupt-controller@40001800 { - compatible = "fsl,vf610-mscm-ir"; - reg = <0x40001800 0x400>; - fsl,cpucfg = <&mscm_cpucfg>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - } diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml new file mode 100644 index 000000000000..fdc254f8d013 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Vybrid Miscellaneous System Control - Interrupt Router + +description: + The MSCM IP contains multiple sub modules, this binding describes the second + block of registers which control the interrupt router. The interrupt router + allows to configure the recipient of each peripheral interrupt. Furthermore + it controls the directed processor interrupts. The module is available in all + Vybrid SoC's but is only really useful in dual core configurations (VF6xx + which comes with a Cortex-A5/Cortex-M4 combination). + + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,vf610-mscm-ir + + reg: + maxItems: 1 + + fsl,cpucfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The handle to the MSCM CPU configuration node, required + to get the current CPU ID + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + Two cells, interrupt number and cells. + The hardware interrupt number according to interrupt + assignment of the interrupt router is required. + Flags get passed only when using GIC as parent. Flags + encoding as documented by the GIC bindings. + +required: + - compatible + - reg + - fsl,cpucfg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@40001800 { + compatible = "fsl,vf610-mscm-ir"; + reg = <0x40001800 0x400>; + fsl,cpucfg = <&mscm_cpucfg>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + }; From 7ef2310b580d617f18ee6e08071294a58eeaca15 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:38 +0200 Subject: [PATCH 30/31] dt-bindings: display: mediatek,dp: Allow DisplayPort AUX bus Like others, the MediaTek DisplayPort controller provides an auxiliary bus: import the common dp-aux-bus.yaml in this binding to allow specifying an aux-bus subnode. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250724083914.61351-3-angelogioacchino.delregno@collabora.com Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/mediatek/mediatek,dp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml index 75ce92f4a5fd..274f590807ca 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -45,6 +45,9 @@ properties: '#sound-dai-cells': const: 0 + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + ports: $ref: /schemas/graph.yaml#/properties/ports properties: From 0121898ec05fa4c1f566fc05c7e8b3caf0998f97 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 25 Jul 2025 12:02:42 +0200 Subject: [PATCH 31/31] dt-bindings: Correct indentation and style in DTS example DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Acked-by: Ulf Hansson # For MMC Acked-by: Lee Jones Acked-by: Thierry Reding Reviewed-by: Geert Uytterhoeven # renesas Link: https://lore.kernel.org/r/20250107131456.247610-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250725100241.120106-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- .../arm/arm,trace-buffer-extension.yaml | 10 +- .../bindings/arm/stm32/st,mlahb.yaml | 20 +- .../bindings/dsp/mediatek,mt8195-dsp.yaml | 42 ++-- ...ntel,ixp4xx-network-processing-engine.yaml | 52 ++--- .../bindings/fpga/xlnx,versal-fpga.yaml | 2 +- .../bindings/iommu/riscv,iommu.yaml | 6 +- .../devicetree/bindings/leds/leds-mt6360.yaml | 195 +++++++++--------- .../devicetree/bindings/mips/brcm/soc.yaml | 42 ++-- .../misc/intel,ixp4xx-ahb-queue-manager.yaml | 6 +- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 78 +++---- .../bindings/mtd/technologic,nand.yaml | 2 +- .../bindings/nvmem/amlogic,meson6-efuse.yaml | 2 +- .../bindings/pci/ti,j721e-pci-ep.yaml | 34 +-- .../bindings/power/reset/qcom,pon.yaml | 62 +++--- .../nvidia,tegra264-bpmp-shmem.yaml | 15 +- .../bindings/rtc/renesas,rzn1-rtc.yaml | 22 +- .../amlogic/amlogic,meson-gx-hhi-sysctrl.yaml | 26 +-- .../bindings/soc/qcom/qcom,eud.yaml | 38 ++-- .../bindings/soc/ti/wkup-m3-ipc.yaml | 32 +-- 19 files changed, 343 insertions(+), 343 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml index 87128e7b7d28..f5b54b4fc55d 100644 --- a/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml +++ b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml @@ -41,10 +41,10 @@ additionalProperties: false examples: - | - #include + #include - trbe { - compatible = "arm,trace-buffer-extension"; - interrupts = ; - }; + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = ; + }; ... diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml index 3e996346b264..4970b9167d1c 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -55,17 +55,17 @@ unevaluatedProperties: false examples: - | ahb { - compatible = "st,mlahb", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - dma-ranges = <0x00000000 0x38000000 0x10000>, - <0x10000000 0x10000000 0x60000>, - <0x30000000 0x30000000 0x60000>; + compatible = "st,mlahb", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; - m4_rproc: m4@10000000 { - reg = <0x10000000 0x40000>; - }; + m4_rproc: m4@10000000 { + reg = <0x10000000 0x40000>; + }; }; ... diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml index ca8d8661f872..abc52978be7a 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml @@ -81,25 +81,25 @@ examples: #include #include dsp@10803000 { - compatible = "mediatek,mt8195-dsp"; - reg = <0x10803000 0x1000>, - <0x10840000 0x40000>; - reg-names = "cfg", "sram"; - clocks = <&topckgen 10>, //CLK_TOP_ADSP - <&clk26m>, - <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS - <&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2 - <&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP - <&topckgen 34>; //CLK_TOP_AUDIO_H - clock-names = "adsp_sel", - "clk26m_ck", - "audio_local_bus", - "mainpll_d7_d2", - "scp_adsp_audiodsp", - "audio_h"; - memory-region = <&adsp_dma_mem_reserved>, - <&adsp_mem_reserved>; - power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP - mbox-names = "rx", "tx"; - mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + compatible = "mediatek,mt8195-dsp"; + reg = <0x10803000 0x1000>, + <0x10840000 0x40000>; + reg-names = "cfg", "sram"; + clocks = <&topckgen 10>, //CLK_TOP_ADSP + <&clk26m>, + <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS + <&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2 + <&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP + <&topckgen 34>; //CLK_TOP_AUDIO_H + clock-names = "adsp_sel", + "clk26m_ck", + "audio_local_bus", + "mainpll_d7_d2", + "scp_adsp_audiodsp", + "audio_h"; + memory-region = <&adsp_dma_mem_reserved>, + <&adsp_mem_reserved>; + power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; }; diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml index e6bed7d93e2d..50f1f08744a1 100644 --- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -62,33 +62,33 @@ examples: #include npe: npe@c8006000 { - compatible = "intel,ixp4xx-network-processing-engine"; - reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; - hss@0 { - compatible = "intel,ixp4xx-hss"; - reg = <0>; - intel,npe-handle = <&npe 0>; - intel,queue-chl-rxtrig = <&qmgr 12>; - intel,queue-chl-txready = <&qmgr 34>; - intel,queue-pkt-rx = <&qmgr 13>; - intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; - intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; - intel,queue-pkt-txdone = <&qmgr 22>; - cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; - clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; - }; + hss@0 { + compatible = "intel,ixp4xx-hss"; + reg = <0>; + intel,npe-handle = <&npe 0>; + intel,queue-chl-rxtrig = <&qmgr 12>; + intel,queue-chl-txready = <&qmgr 34>; + intel,queue-pkt-rx = <&qmgr 13>; + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; + intel,queue-pkt-txdone = <&qmgr 22>; + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; + }; - crypto { - compatible = "intel,ixp4xx-crypto"; - intel,npe-handle = <&npe 2>; - queue-rx = <&qmgr 30>; - queue-txready = <&qmgr 29>; - }; + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; }; ... diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml index 80833462f620..41b368d54557 100644 --- a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml @@ -27,7 +27,7 @@ additionalProperties: false examples: - | versal_fpga: versal-fpga { - compatible = "xlnx,versal-fpga"; + compatible = "xlnx,versal-fpga"; }; ... diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml index 5d015eeb06d0..d4838c3b3741 100644 --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml @@ -139,9 +139,9 @@ examples: /* The IOMMU programming interface uses slot 00:01.0 */ iommu0: iommu@1,0 { - compatible = "pci1efd,edf1", "riscv,pci-iommu"; - reg = <0x800 0 0 0 0>; - #iommu-cells = <1>; + compatible = "pci1efd,edf1", "riscv,pci-iommu"; + reg = <0x800 0 0 0 0>; + #iommu-cells = <1>; }; }; }; diff --git a/Documentation/devicetree/bindings/leds/leds-mt6360.yaml b/Documentation/devicetree/bindings/leds/leds-mt6360.yaml index d84e28e616d7..d2e1d8afc302 100644 --- a/Documentation/devicetree/bindings/leds/leds-mt6360.yaml +++ b/Documentation/devicetree/bindings/leds/leds-mt6360.yaml @@ -87,106 +87,105 @@ additionalProperties: false examples: - | - #include - led-controller { - compatible = "mediatek,mt6360-led"; - #address-cells = <1>; - #size-cells = <0>; + #include + led-controller { + compatible = "mediatek,mt6360-led"; + #address-cells = <1>; + #size-cells = <0>; - multi-led@0 { - reg = <0>; - function = LED_FUNCTION_INDICATOR; - color = ; - led-max-microamp = <24000>; - #address-cells = <1>; - #size-cells = <0>; - led@0 { - reg = <0>; - color = ; - }; - led@1 { - reg = <1>; - color = ; - }; - led@2 { - reg = <2>; - color = ; - }; - }; - led@3 { - reg = <3>; - function = LED_FUNCTION_INDICATOR; - color = ; - led-max-microamp = <150000>; - }; - led@4 { - reg = <4>; - function = LED_FUNCTION_FLASH; - color = ; - function-enumerator = <1>; - led-max-microamp = <200000>; - flash-max-microamp = <500000>; - flash-max-timeout-us = <1024000>; - }; - led@5 { - reg = <5>; - function = LED_FUNCTION_FLASH; - color = ; - function-enumerator = <2>; - led-max-microamp = <200000>; - flash-max-microamp = <500000>; - flash-max-timeout-us = <1024000>; - }; - }; + multi-led@0 { + reg = <0>; + function = LED_FUNCTION_INDICATOR; + color = ; + led-max-microamp = <24000>; + #address-cells = <1>; + #size-cells = <0>; + led@0 { + reg = <0>; + color = ; + }; + led@1 { + reg = <1>; + color = ; + }; + led@2 { + reg = <2>; + color = ; + }; + }; + led@3 { + reg = <3>; + function = LED_FUNCTION_INDICATOR; + color = ; + led-max-microamp = <150000>; + }; + led@4 { + reg = <4>; + function = LED_FUNCTION_FLASH; + color = ; + function-enumerator = <1>; + led-max-microamp = <200000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <1024000>; + }; + led@5 { + reg = <5>; + function = LED_FUNCTION_FLASH; + color = ; + function-enumerator = <2>; + led-max-microamp = <200000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <1024000>; + }; + }; - | + led-controller { + compatible = "mediatek,mt6360-led"; + #address-cells = <1>; + #size-cells = <0>; - led-controller { - compatible = "mediatek,mt6360-led"; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - function = LED_FUNCTION_INDICATOR; - color = ; - led-max-microamp = <24000>; - }; - led@1 { - reg = <1>; - function = LED_FUNCTION_INDICATOR; - color = ; - led-max-microamp = <24000>; - }; - led@2 { - reg = <2>; - function = LED_FUNCTION_INDICATOR; - color = ; - led-max-microamp = <24000>; - }; - led@3 { - reg = <3>; - function = LED_FUNCTION_INDICATOR; - color = ; - led-max-microamp = <150000>; - }; - led@4 { - reg = <4>; - function = LED_FUNCTION_FLASH; - color = ; - function-enumerator = <1>; - led-max-microamp = <200000>; - flash-max-microamp = <500000>; - flash-max-timeout-us = <1024000>; - }; - led@5 { - reg = <5>; - function = LED_FUNCTION_FLASH; - color = ; - function-enumerator = <2>; - led-max-microamp = <200000>; - flash-max-microamp = <500000>; - flash-max-timeout-us = <1024000>; - }; - }; + led@0 { + reg = <0>; + function = LED_FUNCTION_INDICATOR; + color = ; + led-max-microamp = <24000>; + }; + led@1 { + reg = <1>; + function = LED_FUNCTION_INDICATOR; + color = ; + led-max-microamp = <24000>; + }; + led@2 { + reg = <2>; + function = LED_FUNCTION_INDICATOR; + color = ; + led-max-microamp = <24000>; + }; + led@3 { + reg = <3>; + function = LED_FUNCTION_INDICATOR; + color = ; + led-max-microamp = <150000>; + }; + led@4 { + reg = <4>; + function = LED_FUNCTION_FLASH; + color = ; + function-enumerator = <1>; + led-max-microamp = <200000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <1024000>; + }; + led@5 { + reg = <5>; + function = LED_FUNCTION_FLASH; + color = ; + function-enumerator = <2>; + led-max-microamp = <200000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <1024000>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 0cc634482a6a..461a8c063313 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -92,29 +92,29 @@ additionalProperties: true examples: - | - / { - compatible = "brcm,bcm3368"; - #address-cells = <1>; - #size-cells = <1>; - model = "Broadcom 3368"; + / { + compatible = "brcm,bcm3368"; + #address-cells = <1>; + #size-cells = <1>; + model = "Broadcom 3368"; - cpus { - #address-cells = <1>; - #size-cells = <0>; + cpus { + #address-cells = <1>; + #size-cells = <0>; - mips-hpt-frequency = <150000000>; + mips-hpt-frequency = <150000000>; - cpu@0 { - compatible = "brcm,bmips4350"; - device_type = "cpu"; - reg = <0>; - }; + cpu@0 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <0>; + }; - cpu@1 { - compatible = "brcm,bmips4350"; - device_type = "cpu"; - reg = <1>; - }; - }; - }; + cpu@1 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <1>; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml b/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml index 36a9dbdf3f03..aab89946b04f 100644 --- a/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml +++ b/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml @@ -45,7 +45,7 @@ examples: #include qmgr: queue-manager@60000000 { - compatible = "intel,ixp4xx-ahb-queue-manager"; - reg = <0x60000000 0x4000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; + compatible = "intel,ixp4xx-ahb-queue-manager"; + reg = <0x60000000 0x4000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 7563623876fc..2fa2c0bcefed 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -245,49 +245,49 @@ examples: #include sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0xee100000 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee100000 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; }; sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0xee120000 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee120000 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; }; sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0xee140000 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0xee160000 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee140000 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee160000 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; }; diff --git a/Documentation/devicetree/bindings/mtd/technologic,nand.yaml b/Documentation/devicetree/bindings/mtd/technologic,nand.yaml index f9d87c46094b..a3c316436317 100644 --- a/Documentation/devicetree/bindings/mtd/technologic,nand.yaml +++ b/Documentation/devicetree/bindings/mtd/technologic,nand.yaml @@ -40,6 +40,6 @@ examples: #address-cells = <1>; #size-cells = <0>; nand@0 { - reg = <0>; + reg = <0>; }; }; diff --git a/Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml b/Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml index b5cf740f96fa..9879d521842e 100644 --- a/Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml @@ -53,6 +53,6 @@ examples: }; temperature_calib: calib@1f4 { - reg = <0x1f4 0x4>; + reg = <0x1f4 0x4>; }; }; diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 97f2579ea908..29580cbd1767 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -123,21 +123,21 @@ examples: #size-cells = <2>; pcie0_ep: pcie-ep@d000000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - dma-coherent; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - }; + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + }; }; diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml index 3da3d02a6690..979a377cb4ff 100644 --- a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml +++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml @@ -115,40 +115,40 @@ allOf: examples: - | - #include - #include - #include + #include + #include + #include - spmi@c440000 { - reg = <0x0c440000 0x1100>; - #address-cells = <2>; - #size-cells = <0>; + spmi@c440000 { + reg = <0x0c440000 0x1100>; + #address-cells = <2>; + #size-cells = <0>; - pmic@0 { - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; + pmic@0 { + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; - pon@800 { - compatible = "qcom,pm8998-pon"; - reg = <0x800>; + pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - }; - }; + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml index f9b2f0fdc282..4380f622f9a9 100644 --- a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml @@ -36,12 +36,13 @@ required: examples: - | reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - dram_cpu_bpmp_mail: shmem@f1be0000 { - compatible = "nvidia,tegra264-bpmp-shmem"; - reg = <0x0 0xf1be0000 0x0 0x2000>; - no-map; - }; + #address-cells = <2>; + #size-cells = <2>; + + shmem@f1be0000 { + compatible = "nvidia,tegra264-bpmp-shmem"; + reg = <0x0 0xf1be0000 0x0 0x2000>; + no-map; + }; }; ... diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml index f6fdcc7090b6..1860f0e4c31a 100644 --- a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -61,14 +61,14 @@ examples: #include #include rtc@40006000 { - compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; - reg = <0x40006000 0x1000>; - interrupts = , - , - ; - interrupt-names = "alarm", "timer", "pps"; - clocks = <&sysctrl R9A06G032_HCLK_RTC>; - clock-names = "hclk"; - power-domains = <&sysctrl>; - start-year = <2000>; - }; + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = , + , + ; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + start-year = <2000>; + }; diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml index 3dc66f1de023..f3a85c67ce8a 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml @@ -186,22 +186,22 @@ examples: }; power-controller { - compatible = "amlogic,meson-axg-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&sysctrl_AO>; + compatible = "amlogic,meson-axg-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; - resets = <&reset_viu>, - <&reset_venc>, - <&reset_vcbus>, - <&reset_vencl>, - <&reset_vid_lock>; - reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock"; - clocks = <&clk_vpu>, <&clk_vapb>; - clock-names = "vpu", "vapb"; + resets = <&reset_viu>, + <&reset_venc>, + <&reset_vcbus>, + <&reset_vencl>, + <&reset_vid_lock>; + reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock"; + clocks = <&clk_vpu>, <&clk_vapb>; + clock-names = "vpu", "vapb"; }; phy { - compatible = "amlogic,axg-mipi-pcie-analog-phy"; - #phy-cells = <0>; + compatible = "amlogic,axg-mipi-pcie-analog-phy"; + #phy-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437..84218636c0d8 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -55,25 +55,25 @@ additionalProperties: false examples: - | eud@88e0000 { - compatible = "qcom,sc7280-eud", "qcom,eud"; - reg = <0x88e0000 0x2000>, - <0x88e2000 0x1000>; + compatible = "qcom,sc7280-eud", "qcom,eud"; + reg = <0x88e0000 0x2000>, + <0x88e2000 0x1000>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - eud_ep: endpoint { - remote-endpoint = <&usb2_role_switch>; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; - port@1 { - reg = <1>; - eud_con: endpoint { - remote-endpoint = <&con_eud>; - }; - }; - }; + port@1 { + reg = <1>; + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml b/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml index 0df41c4f60c1..56b16183c885 100644 --- a/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml +++ b/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml @@ -121,13 +121,13 @@ examples: }; wkup_m3_ipc@1324 { - compatible = "ti,am3352-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&am335x_mailbox &mbox_wkupm3>; - ti,vtt-gpio-pin = <7>; - firmware-name = "am335x-evm-scale-data.bin"; + compatible = "ti,am3352-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&am335x_mailbox &mbox_wkupm3>; + ti,vtt-gpio-pin = <7>; + firmware-name = "am335x-evm-scale-data.bin"; }; }; @@ -155,20 +155,20 @@ examples: pinctrl-0 = <&ddr3_vtt_toggle_default>; ddr3_vtt_toggle_default: ddr_vtt_toggle_default { - pinctrl-single,pins = < + pinctrl-single,pins = < 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) - >; + >; }; }; wkup_m3_ipc@1324 { - compatible = "ti,am4372-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&am437x_mailbox &mbox_wkupm3>; - ti,set-io-isolation; - firmware-name = "am43x-evm-scale-data.bin"; + compatible = "ti,am4372-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&am437x_mailbox &mbox_wkupm3>; + ti,set-io-isolation; + firmware-name = "am43x-evm-scale-data.bin"; }; };