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dt-bindings: gpio: Convert apm,xgene-gpio-sb to DT schema
Convert APM X-Gene Standby GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202821.3011099-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Rob Herring (Arm)
Bartosz Golaszewski
parent
842dcff8e2
commit
672d644a7d
2 changed files with 94 additions and 64 deletions
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/apm,xgene-gpio-sb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: APM X-Gene Standby GPIO controller
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maintainers:
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- Khuong Dinh <khuong@os.amperecomputing.com>
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description: |
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This is a gpio controller in the standby domain. It also supports interrupt in
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some particular pins which are sourced to its parent interrupt controller
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as diagram below:
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+-----------------+
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| X-Gene standby |
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| GPIO controller +------ GPIO_0
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+------------+ | | ...
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| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
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| controller | (SPI40) | | ...
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| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
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| | ... | |
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| | EXT_INT_N | +------ GPIO_[N+9]
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| | (SPI[40 + N])| | ...
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| +--------------+ +------ GPIO_MAX
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+------------+ +-----------------+
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properties:
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compatible:
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const: apm,xgene-gpio-sb
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reg:
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maxItems: 1
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'#gpio-cells':
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const: 2
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gpio-controller: true
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interrupts:
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description:
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List of interrupt specifiers for EXT_INT_0 through EXT_INT_N. The first
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entry must correspond to EXT_INT_0.
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'#interrupt-cells':
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const: 2
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description:
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First cell selects EXT_INT_N (0-N), second cell specifies flags
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interrupt-controller: true
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apm,nr-gpios:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of GPIO pins
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apm,nr-irqs:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of interrupt pins
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apm,irq-start:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Lowest GPIO pin supporting interrupts
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required:
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- compatible
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- reg
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- '#gpio-cells'
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- gpio-controller
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- interrupts
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- '#interrupt-cells'
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- interrupt-controller
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additionalProperties: false
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examples:
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- |
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gpio@17001000 {
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compatible = "apm,xgene-gpio-sb";
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reg = <0x17001000 0x400>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupts = <0x0 0x28 0x1>,
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<0x0 0x29 0x1>,
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<0x0 0x2a 0x1>,
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<0x0 0x2b 0x1>,
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<0x0 0x2c 0x1>,
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<0x0 0x2d 0x1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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apm,nr-gpios = <22>;
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apm,nr-irqs = <6>;
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apm,irq-start = <8>;
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};
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@ -1,64 +0,0 @@
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APM X-Gene Standby GPIO controller bindings
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This is a gpio controller in the standby domain. It also supports interrupt in
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some particular pins which are sourced to its parent interrupt controller
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as diagram below:
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+-----------------+
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| X-Gene standby |
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| GPIO controller +------ GPIO_0
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+------------+ | | ...
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| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
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| controller | (SPI40) | | ...
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| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
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| | ... | |
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| | EXT_INT_N | +------ GPIO_[N+9]
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| | (SPI[40 + N])| | ...
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| +--------------+ +------ GPIO_MAX
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+------------+ +-----------------+
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Required properties:
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- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
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- reg: Physical base address and size of the controller's registers
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- #gpio-cells: Should be two.
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- first cell is the pin number
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- second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- gpio-controller: Marks the device node as a GPIO controller.
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- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
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- interrupt-cells: Should be two.
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- first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N.
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- second cell is used to specify flags.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- apm,nr-gpios: Optional, specify number of gpios pin.
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- apm,nr-irqs: Optional, specify number of interrupt pins.
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- apm,irq-start: Optional, specify lowest gpio pin support interrupt.
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Example:
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sbgpio: gpio@17001000{
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compatible = "apm,xgene-gpio-sb";
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reg = <0x0 0x17001000 0x0 0x400>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupts = <0x0 0x28 0x1>,
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<0x0 0x29 0x1>,
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<0x0 0x2a 0x1>,
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<0x0 0x2b 0x1>,
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<0x0 0x2c 0x1>,
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<0x0 0x2d 0x1>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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interrupt-controller;
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apm,nr-gpios = <22>;
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apm,nr-irqs = <6>;
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apm,irq-start = <8>;
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};
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testuser {
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compatible = "example,testuser";
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/* Use the GPIO_13/EXT_INT_5 line as an active high triggered
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* level interrupt
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*/
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interrupts = <5 4>;
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interrupt-parent = <&sbgpio>;
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};
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