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arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0

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The MT8188 video decoder pipeline has two hardware IP blocks: LAT and
Core, which are powered by vdec0 and vdec1 power domains, respectively.

The hardware design includes a dependency between the vdec0 and vdec1
power domains to ensure that Core is powered down before LAT. Without
correctly describing this dependency in DT, the system will fail to
suspend.

As a comparable reference, MT8192 also uses the LAT + Core decoding
pipeline, and it has the correct power domain dependency defined in DT.

Update vdec1 as a sub-domain of vdec0 in MT8188 DT to reflect the
hardware design. Also, use more specific clock names for both power
domains.

Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20241001113052.3124869-8-fshao@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Fei Shao 2024-10-01 19:27:25 +08:00 • committed by AngeloGioacchino Del Regno
parent c1134cbf00
commit 66c466dae8
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GPG key ID: 9A3604CFAD978478
1 changed files with 12 additions and 10 deletions
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22
arch/arm64/boot/dts/mediatek/mt8188.dtsi
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@ -1062,20 +1062,22 @@
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_VDEC1 {
reg = <MT8188_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC2_LARB1>;
clock-names = "ss-vdec";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_VDEC0 {
reg = <MT8188_POWER_DOMAIN_VDEC0>;
clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
clock-names = "ss-vdec";
clock-names = "ss-vdec1-soc-l1";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_VDEC1 {
reg = <MT8188_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC2_LARB1>;
clock-names = "ss-vdec2-l1";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {