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arm64: dts: apple: t8011: Add CPU caches

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Add information about CPU caches in the P-cluster of Apple A10X SoC. Due to
"Apple Fusion Architecture" big.LITTLE switcher, only caches from one of
the clusters can be used at any given moment.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-7-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Nick Chan 2025-02-20 20:21:48 +08:00 • committed by Sven Peter
parent a3ffd38110
commit 66be2180e9
1 changed files with 16 additions and 0 deletions
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16
arch/arm64/boot/dts/apple/t8011.dtsi
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@ -36,6 +36,9 @@
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@1 {
@ -46,6 +49,9 @@
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
cpu2: cpu@2 {
@ -56,6 +62,16 @@
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>; /* P-core */
d-cache-size = <0x10000>; /* P-core */
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x800000>; /* P-cluster */
};
};