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arm64: tegra: Add Tegra264 support
Add basic support for the Tegra264 SoC, sufficient for booting into an initial ramdisk. Link: https://lore.kernel.org/r/20250709231401.3767130-2-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding
parent
f1358b1344
commit
65ef237e48
1 changed files with 362 additions and 0 deletions
362
arch/arm64/boot/dts/nvidia/tegra264.dtsi
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362
arch/arm64/boot/dts/nvidia/tegra264.dtsi
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// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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#include <dt-bindings/clock/nvidia,tegra264.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/nvidia,tegra264.h>
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/ {
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compatible = "nvidia,tegra264";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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numa-node-id = <0>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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shmem_bpmp: shmem@86070000 {
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compatible = "nvidia,tegra264-bpmp-shmem";
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reg = <0x0 0x86070000 0x0 0x2000>;
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no-map;
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};
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};
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/* SYSTEM MMIO */
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bus@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;
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misc@100000 {
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compatible = "nvidia,tegra234-misc";
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reg = <0x0 0x00100000 0x0 0x0f000>,
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<0x0 0x0c140000 0x0 0x10000>;
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};
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timer@8000000 {
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compatible = "nvidia,tegra234-timer";
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reg = <0x0 0x08000000 0x0 0x140000>;
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interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gpcdma: dma-controller@8400000 {
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compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
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reg = <0x0 0x08400000 0x0 0x210000>;
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interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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iommus = <&smmu1 0x00000800>;
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dma-coherent;
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dma-channel-mask = <0xfffffffe>;
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status = "disabled";
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};
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hsp_top: hsp@8800000 {
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compatible = "nvidia,tegra264-hsp";
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reg = <0x0 0x08800000 0x0 0xd0000>;
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interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell", "shared0", "shared1", "shared2",
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"shared3", "shared4", "shared5", "shared6",
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"shared7";
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#mbox-cells = <2>;
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};
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rtc: rtc@c2c0000 {
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compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";
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reg = <0x0 0x0c2c0000 0x0 0x10000>;
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interrupt-parent = <&pmc>;
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interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA264_CLK_CLK_S>;
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clock-names = "rtc";
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status = "disabled";
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};
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serial@c4e0000 {
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compatible = "nvidia,tegra264-utc";
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reg = <0x0 0x0c4e0000 0x0 0x8000>,
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<0x0 0x0c4e8000 0x0 0x8000>;
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reg-names = "tx", "rx";
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interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
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rx-threshold = <4>;
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tx-threshold = <4>;
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status = "disabled";
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};
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serial@c5a0000 {
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compatible = "nvidia,tegra264-utc";
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reg = <0x0 0x0c5a0000 0x0 0x8000>,
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<0x0 0x0c5a8000 0x0 0x8000>;
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reg-names = "tx", "rx";
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interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
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rx-threshold = <4>;
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tx-threshold = <4>;
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status = "disabled";
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};
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uart0: serial@c5f0000 {
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compatible = "arm,sbsa-uart";
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reg = <0x0 0x0c5f0000 0x0 0x10000>;
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interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pmc: pmc@c800000 {
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compatible = "nvidia,tegra264-pmc";
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reg = <0x0 0x0c800000 0x0 0x100000>,
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<0x0 0x0c990000 0x0 0x10000>,
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<0x0 0x0ca00000 0x0 0x10000>,
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<0x0 0x0c980000 0x0 0x10000>,
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<0x0 0x0c9c0000 0x0 0x40000>;
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reg-names = "pmc", "wake", "aotag", "scratch", "misc";
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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};
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/* TOP_MMIO */
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bus@8100000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */
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<0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
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<0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
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smmu1: iommu@5000000 {
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compatible = "arm,smmu-v3";
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reg = <0x00 0x5000000 0x0 0x200000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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status = "disabled";
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#iommu-cells = <1>;
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dma-coherent;
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};
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smmu2: iommu@6000000 {
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compatible = "arm,smmu-v3";
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reg = <0x00 0x6000000 0x0 0x200000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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status = "disabled";
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#iommu-cells = <1>;
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dma-coherent;
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};
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smmu0: iommu@a000000 {
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compatible = "arm,smmu-v3";
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reg = <0x00 0xa000000 0x0 0x200000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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status = "disabled";
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#iommu-cells = <1>;
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dma-coherent;
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};
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smmu4: iommu@b000000 {
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compatible = "arm,smmu-v3";
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reg = <0x00 0xb000000 0x0 0x200000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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status = "disabled";
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#iommu-cells = <1>;
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dma-coherent;
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};
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gic: interrupt-controller@46000000 {
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compatible = "arm,gic-v3";
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reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */
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<0x00 0x46080000 0x0 0x400000>; /* GICR */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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redistributor-stride = <0x0 0x40000>;
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#redistributor-regions = <1>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>;
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its: msi-controller@40000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x40000 0x0 0x40000>;
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#msi-cells = <1>;
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msi-controller;
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};
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};
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};
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/* DISP_USB MMIO */
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bus@8800000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
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smmu3: iommu@6000000 {
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compatible = "arm,smmu-v3";
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reg = <0x00 0x6000000 0x0 0x200000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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status = "disabled";
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#iommu-cells = <1>;
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dma-coherent;
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};
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};
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/* UPHY MMIO */
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bus@a800000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
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<0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,armv8";
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device_type = "cpu";
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reg = <0x00000>;
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status = "okay";
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enable-method = "psci";
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numa-node-id = <0>;
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i-cache-size = <65536>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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};
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cpu1: cpu@1 {
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compatible = "arm,armv8";
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device_type = "cpu";
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reg = <0x10000>;
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status = "okay";
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enable-method = "psci";
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numa-node-id = <0>;
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i-cache-size = <65536>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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memory-region = <&shmem_bpmp>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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i2c {
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compatible = "nvidia,tegra186-bpmp-i2c";
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nvidia,bpmp-bus-id = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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thermal {
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compatible = "nvidia,tegra186-bpmp-thermal";
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#thermal-sensor-cells = <1>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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status = "okay";
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};
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psci {
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compatible = "arm,psci-1.0";
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status = "okay";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
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status = "okay";
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};
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};
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