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drm/i915: move force wake support into intel_pm
This commit moves force wake support routines into intel_pm modules, and exports the gen6_gt_check_fifodbg routine (used in I915_READ). Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Eugeni Dodonov
Daniel Vetter
parent
1544d9d573
commit
6590190d12
3 changed files with 192 additions and 191 deletions
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@ -433,197 +433,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
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return 1;
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return 1;
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}
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}
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static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
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{
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u32 gt_thread_status_mask;
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if (IS_HASWELL(dev_priv->dev))
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gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
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else
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gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
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/* w/a for a sporadic read returning 0 by waiting for the GT
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* thread to wake up.
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*/
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if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
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DRM_ERROR("GT thread status wait timed out\n");
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}
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static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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u32 forcewake_ack;
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if (IS_HASWELL(dev_priv->dev))
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forcewake_ack = FORCEWAKE_ACK_HSW;
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else
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forcewake_ack = FORCEWAKE_ACK;
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500))
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DRM_ERROR("Force wake wait timed out\n");
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I915_WRITE_NOTRACE(FORCEWAKE, 1);
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
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DRM_ERROR("Force wake wait timed out\n");
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
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{
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u32 forcewake_ack;
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if (IS_HASWELL(dev_priv->dev))
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forcewake_ack = FORCEWAKE_ACK_HSW;
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else
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forcewake_ack = FORCEWAKE_MT_ACK;
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500))
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DRM_ERROR("Force wake wait timed out\n");
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I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
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DRM_ERROR("Force wake wait timed out\n");
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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/*
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* Generally this is called implicitly by the register read function. However,
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* if some sequence requires the GT to not power down then this function should
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* be called at the beginning of the sequence followed by a call to
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* gen6_gt_force_wake_put() at the end of the sequence.
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*/
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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if (dev_priv->forcewake_count++ == 0)
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dev_priv->gt.force_wake_get(dev_priv);
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
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{
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u32 gtfifodbg;
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gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
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if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
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"MMIO read or write has been dropped %x\n", gtfifodbg))
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I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
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}
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static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE, 0);
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/* The below doubles as a POSTING_READ */
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gen6_gt_check_fifodbg(dev_priv);
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}
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static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
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/* The below doubles as a POSTING_READ */
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gen6_gt_check_fifodbg(dev_priv);
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}
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/*
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* see gen6_gt_force_wake_get()
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*/
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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if (--dev_priv->forcewake_count == 0)
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dev_priv->gt.force_wake_put(dev_priv);
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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int ret = 0;
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if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
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int loop = 500;
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u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
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udelay(10);
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fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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}
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if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
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++ret;
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dev_priv->gt_fifo_count = fifo;
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}
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dev_priv->gt_fifo_count--;
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return ret;
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}
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static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
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{
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/* Already awake? */
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if ((I915_READ(0x130094) & 0xa1) == 0xa1)
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return;
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I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
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POSTING_READ(FORCEWAKE_VLV);
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if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500))
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DRM_ERROR("Force wake wait timed out\n");
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
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/* FIXME: confirm VLV behavior with Punit folks */
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POSTING_READ(FORCEWAKE_VLV);
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}
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void intel_gt_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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spin_lock_init(&dev_priv->gt_lock);
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if (IS_VALLEYVIEW(dev)) {
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dev_priv->gt.force_wake_get = vlv_force_wake_get;
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dev_priv->gt.force_wake_put = vlv_force_wake_put;
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} else if (INTEL_INFO(dev)->gen >= 6) {
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dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
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dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
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/* IVB configs may use multi-threaded forcewake */
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if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
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u32 ecobus;
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/* A small trick here - if the bios hasn't configured
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* MT forcewake, and if the device is in RC6, then
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* force_wake_mt_get will not wake the device and the
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* ECOBUS read will return zero. Which will be
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* (correctly) interpreted by the test below as MT
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* forcewake being disabled.
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*/
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mutex_lock(&dev->struct_mutex);
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__gen6_gt_force_wake_mt_get(dev_priv);
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ecobus = I915_READ_NOTRACE(ECOBUS);
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__gen6_gt_force_wake_mt_put(dev_priv);
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mutex_unlock(&dev->struct_mutex);
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if (ecobus & FORCEWAKE_MT_ENABLE) {
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DRM_DEBUG_KMS("Using MT version of forcewake\n");
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dev_priv->gt.force_wake_get =
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__gen6_gt_force_wake_mt_get;
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dev_priv->gt.force_wake_put =
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__gen6_gt_force_wake_mt_put;
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}
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}
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}
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}
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static int i915_drm_freeze(struct drm_device *dev)
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static int i915_drm_freeze(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -493,6 +493,7 @@ extern void intel_gpu_ips_teardown(void);
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extern void intel_enable_gt_powersave(struct drm_device *dev);
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extern void intel_enable_gt_powersave(struct drm_device *dev);
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extern void intel_disable_gt_powersave(struct drm_device *dev);
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extern void intel_disable_gt_powersave(struct drm_device *dev);
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extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
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extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode);
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extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode);
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extern void intel_ddi_mode_set(struct drm_encoder *encoder,
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extern void intel_ddi_mode_set(struct drm_encoder *encoder,
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@ -3948,3 +3948,194 @@ void intel_init_pm(struct drm_device *dev)
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intel_init_power_wells(dev);
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intel_init_power_wells(dev);
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}
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}
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static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
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{
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u32 gt_thread_status_mask;
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if (IS_HASWELL(dev_priv->dev))
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gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
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else
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gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
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/* w/a for a sporadic read returning 0 by waiting for the GT
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* thread to wake up.
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*/
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if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
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DRM_ERROR("GT thread status wait timed out\n");
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}
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static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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u32 forcewake_ack;
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if (IS_HASWELL(dev_priv->dev))
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forcewake_ack = FORCEWAKE_ACK_HSW;
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else
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forcewake_ack = FORCEWAKE_ACK;
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500))
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DRM_ERROR("Force wake wait timed out\n");
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I915_WRITE_NOTRACE(FORCEWAKE, 1);
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
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DRM_ERROR("Force wake wait timed out\n");
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
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{
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u32 forcewake_ack;
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if (IS_HASWELL(dev_priv->dev))
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forcewake_ack = FORCEWAKE_ACK_HSW;
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else
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forcewake_ack = FORCEWAKE_MT_ACK;
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500))
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DRM_ERROR("Force wake wait timed out\n");
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I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
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if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
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DRM_ERROR("Force wake wait timed out\n");
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__gen6_gt_wait_for_thread_c0(dev_priv);
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}
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/*
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* Generally this is called implicitly by the register read function. However,
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* if some sequence requires the GT to not power down then this function should
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* be called at the beginning of the sequence followed by a call to
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* gen6_gt_force_wake_put() at the end of the sequence.
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*/
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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if (dev_priv->forcewake_count++ == 0)
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dev_priv->gt.force_wake_get(dev_priv);
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
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{
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u32 gtfifodbg;
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gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
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if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
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"MMIO read or write has been dropped %x\n", gtfifodbg))
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I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
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}
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static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE, 0);
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/* The below doubles as a POSTING_READ */
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gen6_gt_check_fifodbg(dev_priv);
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}
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static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
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/* The below doubles as a POSTING_READ */
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gen6_gt_check_fifodbg(dev_priv);
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}
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/*
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* see gen6_gt_force_wake_get()
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*/
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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if (--dev_priv->forcewake_count == 0)
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dev_priv->gt.force_wake_put(dev_priv);
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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int ret = 0;
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if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
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int loop = 500;
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u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
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udelay(10);
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fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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}
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||||||
|
if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
|
||||||
|
++ret;
|
||||||
|
dev_priv->gt_fifo_count = fifo;
|
||||||
|
}
|
||||||
|
dev_priv->gt_fifo_count--;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
|
||||||
|
{
|
||||||
|
/* Already awake? */
|
||||||
|
if ((I915_READ(0x130094) & 0xa1) == 0xa1)
|
||||||
|
return;
|
||||||
|
|
||||||
|
I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
|
||||||
|
POSTING_READ(FORCEWAKE_VLV);
|
||||||
|
|
||||||
|
if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500))
|
||||||
|
DRM_ERROR("Force wake wait timed out\n");
|
||||||
|
|
||||||
|
__gen6_gt_wait_for_thread_c0(dev_priv);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
|
||||||
|
{
|
||||||
|
I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
|
||||||
|
/* FIXME: confirm VLV behavior with Punit folks */
|
||||||
|
POSTING_READ(FORCEWAKE_VLV);
|
||||||
|
}
|
||||||
|
|
||||||
|
void intel_gt_init(struct drm_device *dev)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
spin_lock_init(&dev_priv->gt_lock);
|
||||||
|
|
||||||
|
if (IS_VALLEYVIEW(dev)) {
|
||||||
|
dev_priv->gt.force_wake_get = vlv_force_wake_get;
|
||||||
|
dev_priv->gt.force_wake_put = vlv_force_wake_put;
|
||||||
|
} else if (INTEL_INFO(dev)->gen >= 6) {
|
||||||
|
dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
|
||||||
|
dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
|
||||||
|
|
||||||
|
/* IVB configs may use multi-threaded forcewake */
|
||||||
|
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
|
||||||
|
u32 ecobus;
|
||||||
|
|
||||||
|
/* A small trick here - if the bios hasn't configured
|
||||||
|
* MT forcewake, and if the device is in RC6, then
|
||||||
|
* force_wake_mt_get will not wake the device and the
|
||||||
|
* ECOBUS read will return zero. Which will be
|
||||||
|
* (correctly) interpreted by the test below as MT
|
||||||
|
* forcewake being disabled.
|
||||||
|
*/
|
||||||
|
mutex_lock(&dev->struct_mutex);
|
||||||
|
__gen6_gt_force_wake_mt_get(dev_priv);
|
||||||
|
ecobus = I915_READ_NOTRACE(ECOBUS);
|
||||||
|
__gen6_gt_force_wake_mt_put(dev_priv);
|
||||||
|
mutex_unlock(&dev->struct_mutex);
|
||||||
|
|
||||||
|
if (ecobus & FORCEWAKE_MT_ENABLE) {
|
||||||
|
DRM_DEBUG_KMS("Using MT version of forcewake\n");
|
||||||
|
dev_priv->gt.force_wake_get =
|
||||||
|
__gen6_gt_force_wake_mt_get;
|
||||||
|
dev_priv->gt.force_wake_put =
|
||||||
|
__gen6_gt_force_wake_mt_put;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue