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arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM

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With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for EMMC
on production SOMs and SD on kv260-revB.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf5a4e412e1674500a71a0b1eed7fa8393f37ae9.1683034376.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-05-02 15:35:39 +02:00
parent 4a7f7eadd7
commit 637902f7c4
4 changed files with 7 additions and 1 deletions
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5
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View file

@ -2,7 +2,8 @@
/* /*
* Clock specification for Xilinx ZynqMP * Clock specification for Xilinx ZynqMP
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@xilinx.com>
*/ */
@ -185,10 +186,12 @@
&sdhci0 { &sdhci0 {
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO0_REF>;
}; };
&sdhci1 { &sdhci1 {
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO1_REF>;
}; };
&spi0 { &spi0 {

1
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
View file

@ -132,6 +132,7 @@
no-1-8-v; no-1-8-v;
disable-wp; disable-wp;
xlnx,mio-bank = <1>; xlnx,mio-bank = <1>;
assigned-clock-rates = <187498123>;
}; };
&gem3 { /* required by spec */ &gem3 { /* required by spec */

1
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
View file

@ -115,6 +115,7 @@
clk-phase-sd-hs = <126>, <60>; clk-phase-sd-hs = <126>, <60>;
clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-sdr25 = <120>, <60>;
clk-phase-uhs-ddr50 = <126>, <48>; clk-phase-uhs-ddr50 = <126>, <48>;
assigned-clock-rates = <187498123>;
}; };
&gem3 { /* required by spec */ &gem3 { /* required by spec */

1
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
View file

@ -178,6 +178,7 @@
disable-wp; disable-wp;
bus-width = <8>; bus-width = <8>;
xlnx,mio-bank = <0>; xlnx,mio-bank = <0>;
assigned-clock-rates = <187498123>;
}; };
&spi1 { /* MIO6, 9-11 */ &spi1 { /* MIO6, 9-11 */