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mailbox: tegra: add support for Tegra264

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Tegra264 has a slightly different doorbell register layout than
previous chips.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Stefan Kristiansson 2023-05-29 16:50:45 +03:00 • committed by Jassi Brar
parent af9dbbbb4d
commit 602dbbacc3
1 changed files with 14 additions and 2 deletions
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16
drivers/mailbox/tegra-hsp.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
*/ */
#include <linux/delay.h> #include <linux/delay.h>
@ -97,6 +97,7 @@ struct tegra_hsp_soc {
const struct tegra_hsp_db_map *map; const struct tegra_hsp_db_map *map;
bool has_per_mb_ie; bool has_per_mb_ie;
bool has_128_bit_mb; bool has_128_bit_mb;
unsigned int reg_stride;
}; };
struct tegra_hsp { struct tegra_hsp {
@ -279,7 +280,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
offset += index * 0x100; offset += index * hsp->soc->reg_stride;
db->channel.regs = hsp->regs + offset; db->channel.regs = hsp->regs + offset;
db->channel.hsp = hsp; db->channel.hsp = hsp;
@ -916,24 +917,35 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = {
.map = tegra186_hsp_db_map, .map = tegra186_hsp_db_map,
.has_per_mb_ie = false, .has_per_mb_ie = false,
.has_128_bit_mb = false, .has_128_bit_mb = false,
.reg_stride = 0x100,
}; };
static const struct tegra_hsp_soc tegra194_hsp_soc = { static const struct tegra_hsp_soc tegra194_hsp_soc = {
.map = tegra186_hsp_db_map, .map = tegra186_hsp_db_map,
.has_per_mb_ie = true, .has_per_mb_ie = true,
.has_128_bit_mb = false, .has_128_bit_mb = false,
.reg_stride = 0x100,
}; };
static const struct tegra_hsp_soc tegra234_hsp_soc = { static const struct tegra_hsp_soc tegra234_hsp_soc = {
.map = tegra186_hsp_db_map, .map = tegra186_hsp_db_map,
.has_per_mb_ie = false, .has_per_mb_ie = false,
.has_128_bit_mb = true, .has_128_bit_mb = true,
.reg_stride = 0x100,
};
static const struct tegra_hsp_soc tegra264_hsp_soc = {
.map = tegra186_hsp_db_map,
.has_per_mb_ie = false,
.has_128_bit_mb = true,
.reg_stride = 0x1000,
}; };
static const struct of_device_id tegra_hsp_match[] = { static const struct of_device_id tegra_hsp_match[] = {
{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc }, { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
{ .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc }, { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
{ .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc }, { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
{ .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc },
{ } { }
}; };