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drm/msm/a6xx: Zap counters across context switch

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Any app controlled perfcntr collection (GL_AMD_performance_monitor, etc)
does not require counters to maintain state across context switches.  So
clear them if systemwide profiling is not active.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20220304005317.776110-5-robdclark@gmail.com
This commit is contained in:
Rob Clark 2022-03-03 16:52:17 -08:00
parent 90f45c42d7
commit 5f9ffe8980
1 changed files with 29 additions and 0 deletions
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29
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View file

@ -101,6 +101,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
struct msm_ringbuffer *ring, struct msm_file_private *ctx) struct msm_ringbuffer *ring, struct msm_file_private *ctx)
{ {
bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
phys_addr_t ttbr; phys_addr_t ttbr;
u32 asid; u32 asid;
u64 memptr = rbmemptr(ring, ttbr0); u64 memptr = rbmemptr(ring, ttbr0);
@ -111,6 +112,15 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
return; return;
if (!sysprof) {
/* Turn off protected mode to write to special registers */
OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
OUT_RING(ring, 1);
}
/* Execute the table update */ /* Execute the table update */
OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
@ -137,6 +147,25 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
OUT_PKT7(ring, CP_EVENT_WRITE, 1); OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, 0x31); OUT_RING(ring, 0x31);
if (!sysprof) {
/*
* Wait for SRAM clear after the pgtable update, so the
* two can happen in parallel:
*/
OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));
OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO(
REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS));
OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0));
OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));
OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));
OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));
/* Re-enable protected mode: */
OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
OUT_RING(ring, 1);
}
} }
static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)