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arm64: dts: qcom: x1e80100: Add PCIe nodes
Add nodes for PCIe 4 and 6 controllers and their PHYs for X1E80100 platform. Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-7-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa
Bjorn Andersson
parent
4af46b7bd6
commit
5eb83fc102
1 changed files with 240 additions and 2 deletions
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@ -740,9 +740,9 @@
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clocks = <&bi_tcxo_div2>,
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<&sleep_clk>,
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<0>,
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<&pcie4_phy>,
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<0>,
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<0>,
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<0>,
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<&pcie6a_phy>,
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<0>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
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<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
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@ -2730,6 +2730,244 @@
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#interconnect-cells = <2>;
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};
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pcie6a: pci@1bf8000 {
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device_type = "pci";
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compatible = "qcom,pcie-x1e80100";
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reg = <0 0x01bf8000 0 0x3000>,
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<0 0x70000000 0 0xf1d>,
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<0 0x70000f20 0 0xa8>,
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<0 0x70001000 0 0x1000>,
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<0 0x70100000 0 0x100000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>,
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<0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>;
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bus-range = <0 0xff>;
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dma-coherent;
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linux,pci-domain = <7>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
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<&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
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<&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"noc_aggr",
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"cnoc_sf_axi";
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assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "pcie-mem",
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"cpu-pcie";
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resets = <&gcc GCC_PCIE_6A_BCR>,
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<&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
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reset-names = "pci",
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"link_down";
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power-domains = <&gcc GCC_PCIE_6A_GDSC>;
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phys = <&pcie6a_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie6a_phy: phy@1bfc000 {
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compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
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reg = <0 0x01bfc000 0 0x2000>;
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clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_6A_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe";
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resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
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<&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
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reset-names = "phy",
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"phy_nocsr";
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assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "pcie6a_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie4: pci@1c08000 {
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device_type = "pci";
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compatible = "qcom,pcie-x1e80100";
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reg = <0 0x01c08000 0 0x3000>,
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<0 0x7c000000 0 0xf1d>,
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<0 0x7c000f40 0 0xa8>,
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<0 0x7c001000 0 0x1000>,
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<0 0x7c100000 0 0x100000>,
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<0 0x01c0b000 0 0x1000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config",
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"mhi";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>,
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<0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <5>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
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<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_4_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
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<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"noc_aggr",
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"cnoc_sf_axi";
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assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "pcie-mem",
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"cpu-pcie";
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resets = <&gcc GCC_PCIE_4_BCR>,
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<&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
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reset-names = "pci",
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"link_down";
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power-domains = <&gcc GCC_PCIE_4_GDSC>;
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phys = <&pcie4_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie4_phy: phy@1c0e000 {
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compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
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reg = <0 0x01c0e000 0 0x2000>;
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clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
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<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_4_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe";
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resets = <&gcc GCC_PCIE_4_PHY_BCR>;
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reset-names = "phy";
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assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "pcie4_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0 0x01f40000 0 0x20000>;
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