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Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next

Browse source 
Again, nothing big this time. Mostly a new performance counter from
Christian, some more lockdep annotations from Guido and removal of
functionality that duplicates driver core from Robin.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Lucas Stach <l.stach@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/81367a99b8949584e5becd334ac001b9ad3dc37a.camel@pengutronix.de
This commit is contained in:
Dave Airlie 2020-12-03 13:25:09 +10:00
commit 5eb3c85e34
4 changed files with 59 additions and 27 deletions
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3
drivers/gpu/drm/etnaviv/etnaviv_drv.c
View file

@ -522,7 +522,6 @@ static int etnaviv_bind(struct device *dev)
} }
drm->dev_private = priv; drm->dev_private = priv;
dev->dma_parms = &priv->dma_parms;
dma_set_max_seg_size(dev, SZ_2G); dma_set_max_seg_size(dev, SZ_2G);
mutex_init(&priv->gem_lock); mutex_init(&priv->gem_lock);
@ -572,8 +571,6 @@ static void etnaviv_unbind(struct device *dev)
component_unbind_all(dev, drm); component_unbind_all(dev, drm);
dev->dma_parms = NULL;
etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
drm->dev_private = NULL; drm->dev_private = NULL;

1
drivers/gpu/drm/etnaviv/etnaviv_drv.h
View file

@ -33,7 +33,6 @@ struct etnaviv_file_private {
struct etnaviv_drm_private { struct etnaviv_drm_private {
int num_gpus; int num_gpus;
struct device_dma_parameters dma_parms;
struct etnaviv_gpu *gpu[ETNA_MAX_PIPES]; struct etnaviv_gpu *gpu[ETNA_MAX_PIPES];
gfp_t shm_gfp_mask; gfp_t shm_gfp_mask;

4
drivers/gpu/drm/etnaviv/etnaviv_mmu.c
View file

@ -124,6 +124,8 @@ static void etnaviv_iommu_remove_mapping(struct etnaviv_iommu_context *context,
{ {
struct etnaviv_gem_object *etnaviv_obj = mapping->object; struct etnaviv_gem_object *etnaviv_obj = mapping->object;
lockdep_assert_held(&context->lock);
etnaviv_iommu_unmap(context, mapping->vram_node.start, etnaviv_iommu_unmap(context, mapping->vram_node.start,
etnaviv_obj->sgt, etnaviv_obj->base.size); etnaviv_obj->sgt, etnaviv_obj->base.size);
drm_mm_remove_node(&mapping->vram_node); drm_mm_remove_node(&mapping->vram_node);
@ -216,6 +218,8 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu_context *context,
static int etnaviv_iommu_insert_exact(struct etnaviv_iommu_context *context, static int etnaviv_iommu_insert_exact(struct etnaviv_iommu_context *context,
struct drm_mm_node *node, size_t size, u64 va) struct drm_mm_node *node, size_t size, u64 va)
{ {
lockdep_assert_held(&context->lock);
return drm_mm_insert_node_in_range(&context->mm, node, size, 0, 0, va, return drm_mm_insert_node_in_range(&context->mm, node, size, 0, 0, va,
va + size, DRM_MM_INSERT_LOWEST); va + size, DRM_MM_INSERT_LOWEST);
} }

78
drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
View file

@ -46,6 +46,33 @@ static u32 perf_reg_read(struct etnaviv_gpu *gpu,
return gpu_read(gpu, domain->profile_read); return gpu_read(gpu, domain->profile_read);
} }
static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe)
{
clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(pipe);
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
}
static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu,
const struct etnaviv_pm_domain *domain,
const struct etnaviv_pm_signal *signal)
{
u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
u32 value = 0;
unsigned i;
for (i = 0; i < gpu->identity.pixel_pipes; i++) {
pipe_select(gpu, clock, i);
value += perf_reg_read(gpu, domain, signal);
}
/* switch back to pixel pipe 0 to prevent GPU hang */
pipe_select(gpu, clock, 0);
return value;
}
static u32 pipe_reg_read(struct etnaviv_gpu *gpu, static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_domain *domain,
const struct etnaviv_pm_signal *signal) const struct etnaviv_pm_signal *signal)
@ -55,17 +82,12 @@ static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
unsigned i; unsigned i;
for (i = 0; i < gpu->identity.pixel_pipes; i++) { for (i = 0; i < gpu->identity.pixel_pipes; i++) {
clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); pipe_select(gpu, clock, i);
clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i); value += gpu_read(gpu, signal->data);
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
gpu_write(gpu, domain->profile_config, signal->data);
value += gpu_read(gpu, domain->profile_read);
} }
/* switch back to pixel pipe 0 to prevent GPU hang */ /* switch back to pixel pipe 0 to prevent GPU hang */
clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); pipe_select(gpu, clock, 0);
clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
return value; return value;
} }
@ -103,8 +125,18 @@ static const struct etnaviv_pm_domain doms_3d[] = {
.name = "HI", .name = "HI",
.profile_read = VIVS_MC_PROFILE_HI_READ, .profile_read = VIVS_MC_PROFILE_HI_READ,
.profile_config = VIVS_MC_PROFILE_CONFIG2, .profile_config = VIVS_MC_PROFILE_CONFIG2,
.nr_signals = 5, .nr_signals = 7,
.signal = (const struct etnaviv_pm_signal[]) { .signal = (const struct etnaviv_pm_signal[]) {
{
"TOTAL_READ_BYTES8",
VIVS_HI_PROFILE_READ_BYTES8,
&pipe_reg_read,
},
{
"TOTAL_WRITE_BYTES8",
VIVS_HI_PROFILE_WRITE_BYTES8,
&pipe_reg_read,
},
{ {
"TOTAL_CYCLES", "TOTAL_CYCLES",
0, 0,
@ -141,22 +173,22 @@ static const struct etnaviv_pm_domain doms_3d[] = {
{ {
"PIXEL_COUNT_KILLED_BY_COLOR_PIPE", "PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE, VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"PIXEL_COUNT_KILLED_BY_DEPTH_PIPE", "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE, VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"PIXEL_COUNT_DRAWN_BY_COLOR_PIPE", "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE, VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE", "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE, VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
&pipe_reg_read &pipe_perf_reg_read
} }
} }
}, },
@ -184,32 +216,32 @@ static const struct etnaviv_pm_domain doms_3d[] = {
{ {
"VS_INST_COUNTER", "VS_INST_COUNTER",
VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER, VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"RENDERED_VERTICE_COUNTER", "RENDERED_VERTICE_COUNTER",
VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER, VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"VTX_BRANCH_INST_COUNTER", "VTX_BRANCH_INST_COUNTER",
VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER, VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"VTX_TEXLD_INST_COUNTER", "VTX_TEXLD_INST_COUNTER",
VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER, VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"PXL_BRANCH_INST_COUNTER", "PXL_BRANCH_INST_COUNTER",
VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER, VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"PXL_TEXLD_INST_COUNTER", "PXL_TEXLD_INST_COUNTER",
VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER, VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
} }
} }
}, },
@ -237,17 +269,17 @@ static const struct etnaviv_pm_domain doms_3d[] = {
{ {
"DEPTH_CLIPPED_COUNTER", "DEPTH_CLIPPED_COUNTER",
VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER, VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"TRIVIAL_REJECTED_COUNTER", "TRIVIAL_REJECTED_COUNTER",
VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER, VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
}, },
{ {
"CULLED_COUNTER", "CULLED_COUNTER",
VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER, VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER,
&pipe_reg_read &pipe_perf_reg_read
} }
} }
}, },
@ -400,7 +432,7 @@ static const struct etnaviv_pm_domain doms_2d[] = {
{ {
"PIXELS_RENDERED_2D", "PIXELS_RENDERED_2D",
VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D, VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
&pipe_reg_read &pipe_perf_reg_read
} }
} }
} }