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drm/amd/display: Add PSR SMU Interrupt support

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[WHY]
We have new bios capabilities enabling s0i2 entry on SMU interrupt. We want
this interrupt to be fired on PSR transitions such that we enter s0i2
when entering PSR active.

[HOW]
Add code to send the SMU interrupt with the appropriate
staticscreen flag when entering and exting PSR. Protect this
code with a config flag since it currently impacts BL PWM.

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
SivapiriyanKumarasamy 2018-09-10 18:59:42 -04:00 • committed by Alex Deucher
parent 148cccf267
commit 5d87a3fdce
3 changed files with 16 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
drivers/gpu/drm/amd/display/dc/dc_types.h
View file

@ -550,9 +550,9 @@ struct psr_config {
unsigned char psr_version; unsigned char psr_version;
unsigned int psr_rfb_setup_time; unsigned int psr_rfb_setup_time;
bool psr_exit_link_training_required; bool psr_exit_link_training_required;
bool psr_frame_capture_indication_req; bool psr_frame_capture_indication_req;
unsigned int psr_sdp_transmit_line_num_deadline; unsigned int psr_sdp_transmit_line_num_deadline;
bool allow_smu_optimizations;
}; };
union dmcu_psr_level { union dmcu_psr_level {
@ -654,6 +654,7 @@ struct psr_context {
* continuing powerd own * continuing powerd own
*/ */
unsigned int frame_delay; unsigned int frame_delay;
bool allow_smu_optimizations;
}; };
struct colorspace_transform { struct colorspace_transform {

7
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
View file

@ -213,9 +213,6 @@ static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
psr_context->sdpTransmitLineNumDeadline); psr_context->sdpTransmitLineNumDeadline);
if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
/* waitDMCUReadyForCmd */ /* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
dmcu_wait_reg_ready_interval, dmcu_wait_reg_ready_interval,
@ -594,7 +591,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
psr_context->sdpTransmitLineNumDeadline); psr_context->sdpTransmitLineNumDeadline);
if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) if (psr_context->allow_smu_optimizations)
REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
/* waitDMCUReadyForCmd */ /* waitDMCUReadyForCmd */
@ -615,6 +612,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
psr_context->psrFrameCaptureIndicationReq; psr_context->psrFrameCaptureIndicationReq;
masterCmdData1.bits.aux_chan = psr_context->channel; masterCmdData1.bits.aux_chan = psr_context->channel;
masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
masterCmdData1.u32All); masterCmdData1.u32All);
@ -635,6 +633,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
masterCmdData3.u32All); masterCmdData3.u32All);
/* setDMCUParam_Cmd */ /* setDMCUParam_Cmd */
REG_UPDATE(MASTER_COMM_CMD_REG, REG_UPDATE(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG_BYTE0, PSR_SET); MASTER_COMM_CMD_REG_BYTE0, PSR_SET);

22
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
View file

@ -199,16 +199,16 @@ struct dce_dmcu {
******************************************************************/ ******************************************************************/
union dce_dmcu_psr_config_data_reg1 { union dce_dmcu_psr_config_data_reg1 {
struct { struct {
unsigned int timehyst_frames:8; /*[7:0]*/ unsigned int timehyst_frames:8; /*[7:0]*/
unsigned int hyst_lines:7; /*[14:8]*/ unsigned int hyst_lines:7; /*[14:8]*/
unsigned int rfb_update_auto_en:1; /*[15:15]*/ unsigned int rfb_update_auto_en:1; /*[15:15]*/
unsigned int dp_port_num:3; /*[18:16]*/ unsigned int dp_port_num:3; /*[18:16]*/
unsigned int dcp_sel:3; /*[21:19]*/ unsigned int dcp_sel:3; /*[21:19]*/
unsigned int phy_type:1; /*[22:22]*/ unsigned int phy_type:1; /*[22:22]*/
unsigned int frame_cap_ind:1; /*[23:23]*/ unsigned int frame_cap_ind:1; /*[23:23]*/
unsigned int aux_chan:3; /*[26:24]*/ unsigned int aux_chan:3; /*[26:24]*/
unsigned int aux_repeat:4; /*[30:27]*/ unsigned int aux_repeat:4; /*[30:27]*/
unsigned int reserved:1; /*[31:31]*/ unsigned int allow_smu_optimizations:1; /*[31:31]*/
} bits; } bits;
unsigned int u32All; unsigned int u32All;
}; };
@ -236,7 +236,7 @@ union dce_dmcu_psr_config_data_reg3 {
struct { struct {
unsigned int psr_level:16; /*[15:0]*/ unsigned int psr_level:16; /*[15:0]*/
unsigned int link_rate:4; /*[19:16]*/ unsigned int link_rate:4; /*[19:16]*/
unsigned int reserved:12; /*[31:20]*/ unsigned int reserved:12; /*[31:20]*/
} bits; } bits;
unsigned int u32All; unsigned int u32All;
}; };