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clk: rockchip: Add clock controller driver for RK3528 SoC

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Add clock tree definition for RK3528. Similar to previous Rockchip
SoCs, clock controller of RK3528 is combined with the reset controller.
We omit the reset part for now since it's hard to test it without
support for other basic peripherals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-8-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Yao Zi 2025-02-17 06:11:44 +00:00 • committed by Heiko Stuebner
parent 651aabc9fb
commit 5d0eb375e6
4 changed files with 1142 additions and 0 deletions
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7
drivers/clk/rockchip/Kconfig
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@ -93,6 +93,13 @@ config CLK_RK3399
help help
Build the driver for RK3399 Clock Driver. Build the driver for RK3399 Clock Driver.
config CLK_RK3528
bool "Rockchip RK3528 clock controller support"
depends on ARM64 || COMPILE_TEST
default y
help
Build the driver for RK3528 Clock Controller.
config CLK_RK3568 config CLK_RK3568
bool "Rockchip RK3568 clock controller support" bool "Rockchip RK3568 clock controller support"
depends on ARM64 || COMPILE_TEST depends on ARM64 || COMPILE_TEST

1
drivers/clk/rockchip/Makefile
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@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o

1114
drivers/clk/rockchip/clk-rk3528.c Normal file
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File diff suppressed because it is too large Load diff

20
drivers/clk/rockchip/clk.h
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@ -207,6 +207,26 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK3528_PMU_CRU_BASE 0x10000
#define RK3528_PCIE_CRU_BASE 0x20000
#define RK3528_DDRPHY_CRU_BASE 0x28000
#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
#define RK3528_MODE_CON 0x280
#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
#define RK3528_GLB_CNT_TH 0xc00
#define RK3528_GLB_SRST_FST 0xc08
#define RK3528_GLB_SRST_SND 0xc0c
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x) #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0 #define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4 #define RK3568_MISC_CON0 0xc4