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arm64: zynqmp: Add phase tags marking

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bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-05-02 15:35:51 +02:00
parent 7b91ccd5d2
commit 5be4fbbfbe
3 changed files with 21 additions and 0 deletions
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6
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View file

@ -11,30 +11,35 @@
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
};
video_clk: video_clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
pss_alt_ref_clk: pss_alt_ref_clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
gt_crx_ref_clk: gt_crx_ref_clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
};
aux_ref_clk: aux_ref_clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
@ -43,6 +48,7 @@
&zynqmp_firmware {
zynqmp_clk: clock-controller {
bootph-all;
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,

3
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
View file

@ -236,17 +236,20 @@
&i2c1 {
status = "okay";
bootph-all;
clock-frequency = <400000>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x50>;
/* WP pin EE_WP_EN connected to slg7x644092@68 */
};
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x51>;
};

12
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file

@ -118,6 +118,7 @@
};
zynqmp_ipi: zynqmp_ipi {
bootph-all;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
interrupts = <0 35 4>;
@ -127,6 +128,7 @@
ranges;
ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
@ -143,6 +145,7 @@
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
bootph-all;
};
pmu {
@ -164,8 +167,10 @@
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
method = "smc";
bootph-all;
zynqmp_power: zynqmp-power {
bootph-all;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
interrupts = <0 35 4>;
@ -245,6 +250,7 @@
amba: axi {
compatible = "simple-bus";
bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -684,6 +690,7 @@
};
qspi: spi@ff0f0000 {
bootph-all;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
@ -730,6 +737,7 @@
};
sdhci0: mmc@ff160000 {
bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
@ -744,6 +752,7 @@
};
sdhci1: mmc@ff170000 {
bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
@ -836,6 +845,7 @@
};
uart0: serial@ff000000 {
bootph-all;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
@ -846,6 +856,7 @@
};
uart1: serial@ff010000 {
bootph-all;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
@ -967,6 +978,7 @@
};
zynqmp_dpsub: display@fd4a0000 {
bootph-all;
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,