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ARM: at91: pm: Simplify at91rm9200_standby
Since 2008, AT91_MC_SDRAMC_LPR is set to 0 at kernel initialization. There is no use saving, changing and restoring it. Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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1 changed files with 3 additions and 8 deletions
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@ -222,20 +222,15 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
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*/
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*/
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static void at91rm9200_standby(void)
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static void at91rm9200_standby(void)
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{
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{
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u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
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asm volatile(
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asm volatile(
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"b 1f\n\t"
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"b 1f\n\t"
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".align 5\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %0, [%1, %2]\n\t"
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" str %2, [%1, %3]\n\t"
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" str %3, [%1, %4]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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:
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: "r" (0), "r" (pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR),
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: "r" (0), "r" (pm_data.ramc[0]),
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"r" (1), "r" (AT91_MC_SDRAMC_SRR),
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"r" (1), "r" (AT91_MC_SDRAMC_SRR));
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"r" (lpr));
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}
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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