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riscv: dts: spacemit: add gpio support for K1 SoC

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Populate the GPIO node in the device tree for SpacemiT K1 SoC.
Each of 32 pins will act as one bank and map pins to pinctrl controller.

Link: https://lore.kernel.org/r/20250424-03-k1-gpio-v9-2-eaece8cc5a86@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Yixun Lan 2025-04-24 17:40:50 +08:00
parent 3b2802c2d6
commit 5933312899
No known key found for this signature in database
GPG key ID: 31AAEA47594DBBED
2 changed files with 21 additions and 0 deletions
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3
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
View file

@ -7,6 +7,9 @@
#define K1_PADCONF(pin, func) (((pin) << 16) | (func)) #define K1_PADCONF(pin, func) (((pin) << 16) | (func))
/* Map GPIO pin to each bank's <index, offset> */
#define K1_GPIO(x) (x / 32) (x % 32)
&pinctrl { &pinctrl {
uart0_2_cfg: uart0-2-cfg { uart0_2_cfg: uart0-2-cfg {
uart0-2-pins { uart0-2-pins {

18
arch/riscv/boot/dts/spacemit/k1.dtsi
View file

@ -465,6 +465,24 @@
status = "disabled"; status = "disabled";
}; };
gpio: gpio@d4019000 {
compatible = "spacemit,k1-gpio";
reg = <0x0 0xd4019000 0x0 0x100>;
clocks = <&syscon_apbc CLK_GPIO>,
<&syscon_apbc CLK_GPIO_BUS>;
clock-names = "core", "bus";
gpio-controller;
#gpio-cells = <3>;
interrupts = <58>;
interrupt-parent = <&plic>;
interrupt-controller;
#interrupt-cells = <3>;
gpio-ranges = <&pinctrl 0 0 0 32>,
<&pinctrl 1 0 32 32>,
<&pinctrl 2 0 64 32>,
<&pinctrl 3 0 96 32>;
};
pinctrl: pinctrl@d401e000 { pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl"; compatible = "spacemit,k1-pinctrl";
reg = <0x0 0xd401e000 0x0 0x400>; reg = <0x0 0xd401e000 0x0 0x400>;