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drm/i915: Tidy execlists_init_reg_state
Compact the name of the macro and reg_state variable, and cache some data in local variables to make the function more compact and more readable. v2: Fixup some checkpatch warnings. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/20170221095839.30525-1-tvrtko.ursulin@linux.intel.com
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e2989f140e
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1 changed files with 56 additions and 71 deletions
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@ -190,7 +190,7 @@
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#define CTX_R_PWR_CLK_STATE 0x42
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#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
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#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
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#define CTX_REG(reg_state, pos, reg, val) do { \
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(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
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(reg_state)[(pos)+1] = (val); \
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} while (0)
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@ -1812,104 +1812,89 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
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return indirect_ctx_offset;
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}
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static void execlists_init_reg_state(u32 *reg_state,
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static void execlists_init_reg_state(u32 *regs,
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struct i915_gem_context *ctx,
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struct intel_engine_cs *engine,
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struct intel_ring *ring)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
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u32 base = engine->mmio_base;
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bool rcs = engine->id == RCS;
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/* A context is actually a big batch buffer with several
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* MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
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* values we are setting here are only for the first context restore:
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* on a subsequent save, the GPU will recreate this batchbuffer with new
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* values (including all the missing MI_LOAD_REGISTER_IMM commands that
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* we are not initializing here).
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*/
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regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
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MI_LRI_FORCE_POSTED;
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CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
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_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
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CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
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(HAS_RESOURCE_STREAMER(dev_priv) ?
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CTX_CTRL_RS_CTX_ENABLE : 0)));
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CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
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CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
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CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
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CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
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RING_CTL_SIZE(ring->size) | RING_VALID);
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CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
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CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
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CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
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CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
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CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
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CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
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if (rcs) {
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CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
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CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
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CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
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RING_INDIRECT_CTX_OFFSET(base), 0);
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/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
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* commands followed by (reg, value) pairs. The values we are setting here are
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* only for the first context restore: on a subsequent save, the GPU will
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* recreate this batchbuffer with new values (including all the missing
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* MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
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reg_state[CTX_LRI_HEADER_0] =
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MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
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ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
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RING_CONTEXT_CONTROL(engine),
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_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
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CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
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(HAS_RESOURCE_STREAMER(dev_priv) ?
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CTX_CTRL_RS_CTX_ENABLE : 0)));
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ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
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RING_START(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
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RING_CTL(engine->mmio_base),
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RING_CTL_SIZE(ring->size) | RING_VALID);
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ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
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RING_BBADDR_UDW(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
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RING_BBADDR(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
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RING_BBSTATE(engine->mmio_base),
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RING_BB_PPGTT);
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ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
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RING_SBBADDR_UDW(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
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RING_SBBADDR(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
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RING_SBBSTATE(engine->mmio_base), 0);
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if (engine->id == RCS) {
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ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
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RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
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RING_INDIRECT_CTX(engine->mmio_base), 0);
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ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
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RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
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if (engine->wa_ctx.vma) {
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struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
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u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
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reg_state[CTX_RCS_INDIRECT_CTX+1] =
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regs[CTX_RCS_INDIRECT_CTX + 1] =
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(ggtt_offset + wa_ctx->indirect_ctx.offset) |
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(wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
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reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
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regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
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intel_lr_indirect_ctx_offset(engine) << 6;
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reg_state[CTX_BB_PER_CTX_PTR+1] =
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regs[CTX_BB_PER_CTX_PTR + 1] =
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(ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
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}
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}
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reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
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ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
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RING_CTX_TIMESTAMP(engine->mmio_base), 0);
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regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
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CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
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/* PDP values well be assigned later if needed */
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ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
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0);
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ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
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0);
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CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
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CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
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CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
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CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
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CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
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CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
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CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
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CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
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if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
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/* 64b PPGTT (48bit canonical)
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* PDP0_DESCRIPTOR contains the base address to PML4 and
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* other PDP Descriptors are ignored.
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*/
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ASSIGN_CTX_PML4(ppgtt, reg_state);
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ASSIGN_CTX_PML4(ppgtt, regs);
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}
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if (engine->id == RCS) {
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reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
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ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
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make_rpcs(dev_priv));
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if (rcs) {
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regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
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CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
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make_rpcs(dev_priv));
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}
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}
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