mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
arm64: dts: rockchip: add MNT Reform 2 laptop
MNT Reform 2 is an open source laptop with replaceable CPU modules, including a version with the RK3588-based MNT RCORE[1], which is based on Firefly's iCore-3588Q SoM: - Rockchip RK3588 - Quad A76 and Quad A55 CPU - 6 TOPS NPU - up to 32GB LPDDR4x RAM - SD Card slot - Gigabit ethernet port - HDMI port - 2x mPCIe ports for WiFi or NVMe - 3x USB 3.0 Type-A HOST port [1] https://shop.mntre.com/products/mnt-reform Co-developed-by: "Lukas F. Hartmann" <lukas@mntre.com> Signed-off-by: "Lukas F. Hartmann" <lukas@mntre.com> Signed-off-by: Patrick Wildt <patrick@blueri.se> Link: https://lore.kernel.org/r/Z8S6uDM634KJuyKP@windev.fritz.box Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Patrick Wildt
Heiko Stuebner
parent
3bf4fc44c6
commit
5324af2d02
3 changed files with 780 additions and 0 deletions
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@ -152,6 +152,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb
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443
arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi
Normal file
443
arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi
Normal file
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@ -0,0 +1,443 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3588.dtsi"
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/ {
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compatible = "firefly,icore-3588q", "rockchip,rk3588";
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aliases {
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mmc0 = &sdhci;
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};
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};
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&cpu_b0 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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};
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&cpu_b1 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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};
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&cpu_b2 {
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cpu-supply = <&vdd_cpu_big1_s0>;
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};
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&cpu_b3 {
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cpu-supply = <&vdd_cpu_big1_s0>;
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};
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&cpu_l0 {
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cpu-supply = <&vdd_cpu_lit_s0>;
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};
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&cpu_l1 {
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cpu-supply = <&vdd_cpu_lit_s0>;
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};
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&cpu_l2 {
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cpu-supply = <&vdd_cpu_lit_s0>;
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};
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&cpu_l3 {
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cpu-supply = <&vdd_cpu_lit_s0>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0m2_xfer>;
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status = "okay";
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vdd_cpu_big0_s0: regulator@42 {
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compatible = "rockchip,rk8602";
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reg = <0x42>;
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fcs,suspend-voltage-selector = <1>;
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <1050000>;
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regulator-name = "vdd_cpu_big0_s0";
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc5v0_sys>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_cpu_big1_s0: regulator@43 {
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compatible = "rockchip,rk8603", "rockchip,rk8602";
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reg = <0x43>;
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fcs,suspend-voltage-selector = <1>;
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <1050000>;
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regulator-name = "vdd_cpu_big1_s0";
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc5v0_sys>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1m2_xfer>;
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status = "okay";
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vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
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compatible = "rockchip,rk8602";
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reg = <0x42>;
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fcs,suspend-voltage-selector = <1>;
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <950000>;
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regulator-name = "vdd_npu_s0";
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc5v0_sys>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&sdhci {
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bus-width = <8>;
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no-sdio;
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no-sd;
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non-removable;
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max-frequency = <150000000>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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status = "okay";
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};
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&spi2 {
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assigned-clocks = <&cru CLK_SPI2>;
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assigned-clock-rates = <200000000>;
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num-cs = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
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status = "okay";
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pmic@0 {
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compatible = "rockchip,rk806";
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reg = <0x0>;
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interrupt-parent = <&gpio0>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
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<&rk806_dvs2_null>, <&rk806_dvs3_null>;
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spi-max-frequency = <1000000>;
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system-power-controller;
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vcc1-supply = <&vcc5v0_sys>;
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vcc2-supply = <&vcc5v0_sys>;
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vcc3-supply = <&vcc5v0_sys>;
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vcc4-supply = <&vcc5v0_sys>;
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vcc5-supply = <&vcc5v0_sys>;
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vcc6-supply = <&vcc5v0_sys>;
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vcc7-supply = <&vcc5v0_sys>;
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vcc8-supply = <&vcc5v0_sys>;
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vcc9-supply = <&vcc5v0_sys>;
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vcc10-supply = <&vcc5v0_sys>;
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vcc11-supply = <&vcc_2v0_pldo_s3>;
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vcc12-supply = <&vcc5v0_sys>;
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vcc13-supply = <&vcc_1v1_nldo_s3>;
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vcc14-supply = <&vcc_1v1_nldo_s3>;
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vcca-supply = <&vcc5v0_sys>;
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rk806_dvs1_null: dvs1-null-pins {
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pins = "gpio_pwrctrl1";
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function = "pin_fun0";
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};
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rk806_dvs2_null: dvs2-null-pins {
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pins = "gpio_pwrctrl2";
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function = "pin_fun0";
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};
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rk806_dvs3_null: dvs3-null-pins {
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pins = "gpio_pwrctrl3";
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function = "pin_fun0";
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};
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regulators {
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vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <950000>;
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regulator-ramp-delay = <12500>;
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regulator-name = "vdd_gpu_s0";
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regulator-enable-ramp-delay = <400>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <950000>;
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regulator-ramp-delay = <12500>;
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regulator-name = "vdd_cpu_lit_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_log_s0: dcdc-reg3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <675000>;
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regulator-max-microvolt = <750000>;
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regulator-ramp-delay = <12500>;
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regulator-name = "vdd_log_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <750000>;
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};
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};
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vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <950000>;
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regulator-ramp-delay = <12500>;
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regulator-name = "vdd_vdenc_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_ddr_s0: dcdc-reg5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <675000>;
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regulator-max-microvolt = <950000>;
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regulator-ramp-delay = <12500>;
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regulator-name = "vdd_ddr_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <850000>;
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};
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};
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vdd2_ddr_s3: dcdc-reg6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vdd2_ddr_s3";
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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vcc_2v0_pldo_s3: dcdc-reg7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <2000000>;
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regulator-max-microvolt = <2000000>;
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regulator-name = "vdd_2v0_pldo_s3";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <2000000>;
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};
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};
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vcc_3v3_s3: dcdc-reg8 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc_3v3_s3";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vddq_ddr_s0: dcdc-reg9 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vddq_ddr_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc_1v8_s3: dcdc-reg10 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc_1v8_s3";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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avcc_1v8_s0: pldo-reg1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "avcc_1v8_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc_1v8_s0: pldo-reg2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc_1v8_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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avdd_1v2_s0: pldo-reg3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-name = "avdd_1v2_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc_3v3_s0: pldo-reg4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc_3v3_s0";
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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vccio_sd_s0: pldo-reg5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vccio_sd_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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pldo6_s3: pldo-reg6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "pldo6_s3";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vdd_0v75_s3: nldo-reg1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <750000>;
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regulator-name = "vdd_0v75_s3";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <750000>;
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};
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};
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vdd_ddr_pll_s0: nldo-reg2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <850000>;
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regulator-name = "vdd_ddr_pll_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <850000>;
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};
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};
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avdd_0v75_s0: nldo-reg3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <750000>;
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regulator-name = "avdd_0v75_s0";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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||||
};
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||||
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vdd_0v85_s0: nldo-reg4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <850000>;
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regulator-name = "vdd_0v85_s0";
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||||
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||||
regulator-state-mem {
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regulator-off-in-suspend;
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};
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||||
};
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||||
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vdd_0v75_s0: nldo-reg5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <750000>;
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||||
regulator-max-microvolt = <750000>;
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regulator-name = "vdd_0v75_s0";
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||||
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||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
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||||
};
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||||
};
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||||
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&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
336
arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts
Normal file
336
arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts
Normal file
|
|
@ -0,0 +1,336 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
* Copyright (c) 2024 MNT Research GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
|
||||
#include "rk3588-firefly-icore-3588q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MNT Reform 2 with RCORE RK3588 Module";
|
||||
compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588";
|
||||
chassis-type = "laptop";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
brightness-levels = <0 8 16 32 64 128 160 200 255>;
|
||||
default-brightness-level = <128>;
|
||||
enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pwms = <&pwm8 0 10000 0>;
|
||||
};
|
||||
|
||||
gmac0_clkin: external-gmac0-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "gmac0_clkin";
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
vin-supply = <&avcc_1v8_s0>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v75: regulator-pcie30-avdd0v75 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "pcie30_avdd0v75";
|
||||
vin-supply = <&avdd_0v75_s0>;
|
||||
};
|
||||
|
||||
vcc12v_dcin: regulator-vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_host: regulator-vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
};
|
||||
|
||||
vcc5v0_sys: regulator-vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: regulator-vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus
|
||||
&gmac0_clkinout
|
||||
ð_phy_reset>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu_s0>;
|
||||
sram-supply = <&vdd_gpu_mem_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0_in {
|
||||
hdmi0_in_vp2: endpoint {
|
||||
remote-endpoint = <&vp2_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdptxphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6m0_xfer>;
|
||||
status = "okay";
|
||||
|
||||
rtc@68 {
|
||||
compatible = "nxp,pcf8523";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1l2 {
|
||||
pinctrl-0 = <&pcie2_0_rst>;
|
||||
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie3_reset>;
|
||||
reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
dp {
|
||||
dp1_hpd: dp1-hpd {
|
||||
rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2 {
|
||||
pcie2_0_rst: pcie2-0-rst {
|
||||
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3 {
|
||||
pcie3_reset: pcie3-reset {
|
||||
rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
eth_phy {
|
||||
eth_phy_reset: eth-phy-reset {
|
||||
rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm8 {
|
||||
pinctrl-0 = <&pwm8m2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&avcc_1v8_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
max-frequency = <40000000>;
|
||||
no-1-8-v;
|
||||
no-mmc;
|
||||
no-sdio;
|
||||
vmmc-supply = <&vcc3v3_pcie30>;
|
||||
vqmmc-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp2 {
|
||||
vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi0_in_vp2>;
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue