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ARM: vexpress/tc2: Add interrupt-affinity to the PMU node

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Commit 9fd85eb502 ("ARM: pmu: add support for interrupt-affinity
property") added an optional "interrupt-affinity" property, to specify
the CPU affinity for each SPI listed in the interrupts property.

Without this property, we get this boot warning:

  CPU PMU: Failed to parse <no-node>/interrupt-affinity[0]

This patch adds interrupt-affinity to the PMU node in the
vexpress-ca15_a7(a.k.a TC2) device tree.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Sudeep Holla 2015-05-07 15:45:05 +01:00 • committed by Arnd Bergmann
parent 613880a121
commit 51ef519cbd
1 changed files with 1 additions and 0 deletions
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arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
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@ -191,6 +191,7 @@
compatible = "arm,cortex-a15-pmu"; compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>, interrupts = <0 68 4>,
<0 69 4>; <0 69 4>;
interrupt-affinity = <&cpu0>, <&cpu1>;
}; };
oscclk6a: oscclk6a { oscclk6a: oscclk6a {