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arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106

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Enable psgtr driver and write clocks property to get sata to work.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/80b52ef97501968ee97fc152363bc4b9b7bb2cff.1611224800.git.michal.simek@xilinx.com
This commit is contained in:
Michal Simek 2021-01-21 11:26:53 +01:00
parent 42cb66dcd5
commit 51733f16c6
4 changed files with 58 additions and 0 deletions
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10
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View file

@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
@ -663,6 +664,13 @@
status = "okay";
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -678,6 +686,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */

28
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View file

@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU104 RevA";
@ -36,6 +37,24 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can1 {
@ -158,6 +177,13 @@
status = "okay";
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
@ -169,6 +195,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */

10
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View file

@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU106 RevA";
@ -658,6 +659,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -673,6 +681,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */

10
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View file

@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU111 RevA";
@ -541,6 +542,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -556,6 +564,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */