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drm/amd/display: DP link validation bug for YUV422
remove limit YUV422 color depth to 24bits which is workaround for old ASIC Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 21 additions and 26 deletions
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@ -1379,34 +1379,29 @@ static uint32_t bandwidth_in_kbps_from_timing(
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uint32_t bits_per_channel = 0;
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uint32_t kbps;
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if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
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switch (timing->display_color_depth) {
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case COLOR_DEPTH_666:
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bits_per_channel = 6;
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break;
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case COLOR_DEPTH_888:
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bits_per_channel = 8;
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break;
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case COLOR_DEPTH_101010:
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bits_per_channel = 10;
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break;
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case COLOR_DEPTH_121212:
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bits_per_channel = 12;
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else{
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switch (timing->display_color_depth) {
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case COLOR_DEPTH_666:
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bits_per_channel = 6;
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break;
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case COLOR_DEPTH_888:
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bits_per_channel = 8;
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break;
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case COLOR_DEPTH_101010:
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bits_per_channel = 10;
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break;
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case COLOR_DEPTH_121212:
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bits_per_channel = 12;
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break;
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case COLOR_DEPTH_141414:
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bits_per_channel = 14;
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break;
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case COLOR_DEPTH_161616:
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bits_per_channel = 16;
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break;
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default:
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break;
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}
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break;
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case COLOR_DEPTH_141414:
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bits_per_channel = 14;
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break;
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case COLOR_DEPTH_161616:
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bits_per_channel = 16;
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break;
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default:
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break;
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}
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ASSERT(bits_per_channel != 0);
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kbps = timing->pix_clk_khz;
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