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arm64: dts: renesas: r8a779g0: Add CAN-FD node

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Add device nodes for the CAN-FD interface and the related external CAN
clock on the Renesas R-Car V4H (R8A779G0) SoC.

Based on a patch in the BSP by Kazuya Mizuguch.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6c55d0995089917216ee261a8b8cbb980c7b5304.1674500205.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2023-01-23 20:06:18 +01:00
parent a17039b630
commit 5056a0c728
1 changed files with 57 additions and 0 deletions
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57
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View file

@ -14,6 +14,13 @@
#address-cells = <2>;
#size-cells = <2>;
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -682,6 +689,56 @@
status = "disabled";
};
canfd: can@e6660000 {
compatible = "renesas,r8a779g0-canfd",
"renesas,rcar-gen4-canfd";
reg = <0 0xe6660000 0 0x8500>;
interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 328>,
<&cpg CPG_CORE R8A779G0_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
channel2 {
status = "disabled";
};
channel3 {
status = "disabled";
};
channel4 {
status = "disabled";
};
channel5 {
status = "disabled";
};
channel6 {
status = "disabled";
};
channel7 {
status = "disabled";
};
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";