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net: phy: dp83822: Replace DP83822_DEVADDR with MDIO_MMD_VEND2
Instead of using DP83822_DEVADDR which is locally defined use MDIO_MMD_VEND2. Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20241209-dp83822-mdio-mmd-vend2-v1-1-4473c7284b94@liebherr.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Dimitri Fedrau
Jakub Kicinski
parent
6bb6ab852c
commit
4eb0308d78
1 changed files with 28 additions and 30 deletions
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@ -22,8 +22,6 @@
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#define DP83826C_PHY_ID 0x2000a130
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#define DP83826NC_PHY_ID 0x2000a110
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#define DP83822_DEVADDR 0x1f
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#define MII_DP83822_CTRL_2 0x0a
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#define MII_DP83822_PHYSTS 0x10
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#define MII_DP83822_PHYSCR 0x11
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@ -159,14 +157,14 @@ static int dp83822_config_wol(struct phy_device *phydev,
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/* MAC addresses start with byte 5, but stored in mac[0].
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* 822 PHYs store bytes 4|5, 2|3, 0|1
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*/
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
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phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1,
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(mac[1] << 8) | mac[0]);
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
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phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2,
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(mac[3] << 8) | mac[2]);
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
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phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3,
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(mac[5] << 8) | mac[4]);
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value = phy_read_mmd(phydev, DP83822_DEVADDR,
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value = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_WOL_CFG);
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if (wol->wolopts & WAKE_MAGIC)
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value |= DP83822_WOL_MAGIC_EN;
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@ -174,13 +172,13 @@ static int dp83822_config_wol(struct phy_device *phydev,
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value &= ~DP83822_WOL_MAGIC_EN;
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if (wol->wolopts & WAKE_MAGICSECURE) {
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phy_write_mmd(phydev, DP83822_DEVADDR,
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phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
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phy_write_mmd(phydev, DP83822_DEVADDR,
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phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP2,
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(wol->sopass[3] << 8) | wol->sopass[2]);
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phy_write_mmd(phydev, DP83822_DEVADDR,
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phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP3,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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value |= DP83822_WOL_SECURE_ON;
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@ -194,10 +192,10 @@ static int dp83822_config_wol(struct phy_device *phydev,
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value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
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DP83822_WOL_CLR_INDICATION;
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return phy_write_mmd(phydev, DP83822_DEVADDR,
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return phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_WOL_CFG, value);
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} else {
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return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
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return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_WOL_CFG,
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DP83822_WOL_EN |
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DP83822_WOL_MAGIC_EN |
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@ -226,23 +224,23 @@ static void dp83822_get_wol(struct phy_device *phydev,
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wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
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wol->wolopts = 0;
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
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value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
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if (value & DP83822_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
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if (value & DP83822_WOL_SECURE_ON) {
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
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sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP1);
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
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sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP2);
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
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sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP3);
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
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@ -430,18 +428,18 @@ static int dp83822_config_init(struct phy_device *phydev)
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if (tx_int_delay <= 0)
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rgmii_delay |= DP83822_TX_CLK_SHIFT;
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err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
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err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
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DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
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if (err)
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return err;
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err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
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err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
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if (err)
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return err;
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} else {
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err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
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err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
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if (err)
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@ -496,7 +494,7 @@ static int dp83822_config_init(struct phy_device *phydev)
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return err;
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if (dp83822->fx_signal_det_low) {
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err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
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err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_GENCFG,
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DP83822_SIG_DET_LOW);
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if (err)
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@ -514,10 +512,10 @@ static int dp8382x_config_rmii_mode(struct phy_device *phydev)
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if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) {
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if (strcmp(of_val, "master") == 0) {
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ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
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ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
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DP83822_RMII_MODE_SEL);
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} else if (strcmp(of_val, "slave") == 0) {
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ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
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ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
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DP83822_RMII_MODE_SEL);
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} else {
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phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",
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@ -539,7 +537,7 @@ static int dp83826_config_init(struct phy_device *phydev)
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int ret;
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if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
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ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
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ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
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DP83822_RMII_MODE_EN);
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if (ret)
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return ret;
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@ -548,7 +546,7 @@ static int dp83826_config_init(struct phy_device *phydev)
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if (ret)
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return ret;
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} else {
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ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
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ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
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DP83822_RMII_MODE_EN);
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if (ret)
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return ret;
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@ -560,7 +558,7 @@ static int dp83826_config_init(struct phy_device *phydev)
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FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
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dp83822->cfg_dac_minus));
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mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
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ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val);
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val);
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if (ret)
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return ret;
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@ -568,7 +566,7 @@ static int dp83826_config_init(struct phy_device *phydev)
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FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
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dp83822->cfg_dac_minus));
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mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
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ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
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if (ret)
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return ret;
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}
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@ -577,7 +575,7 @@ static int dp83826_config_init(struct phy_device *phydev)
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val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
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FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
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mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
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ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
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if (ret)
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return ret;
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}
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@ -673,7 +671,7 @@ static int dp83822_read_straps(struct phy_device *phydev)
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int fx_enabled, fx_sd_enable;
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int val;
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val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
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val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1);
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if (val < 0)
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return val;
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@ -748,7 +746,7 @@ static int dp83822_suspend(struct phy_device *phydev)
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{
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int value;
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
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value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
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if (!(value & DP83822_WOL_EN))
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genphy_suspend(phydev);
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@ -762,9 +760,9 @@ static int dp83822_resume(struct phy_device *phydev)
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genphy_resume(phydev);
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
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value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
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phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value |
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DP83822_WOL_CLR_INDICATION);
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return 0;
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