arm64: zynqmp: Switch to amd.com emails

Update my and DPs email address to match current setup. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
2025-09-18 22:14:16 +00:00 · 2023-05-30 12:42:41 +02:00 · 2023-05-30 12:42:41 +02:00 · 4e4ddd3d1d
commit 4e4ddd3d1d
parent f5c8855de1
24 changed files with 27 additions and 27 deletions
--- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
+++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2018, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@ -5,7 +5,7 @@
 * (C) Copyright 2017 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
@ -9,7 +9,7 @@
 * "Y" - A01 board modified with legacy interposer (Nexperia)
 * "Z" - A01 board modified with Diode interposer
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/gpio/gpio.h>
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include <dt-bindings/gpio/gpio.h>
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2020 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-sm-k26-revA.dts"
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 * Nathalie Chan King Choy
 */

--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2018, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu102-revB.dts"
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2020, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu102-rev1.0.dts"
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 #include "zynqmp-zcu102-revA.dts"
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts
@ -4,8 +4,8 @@
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
 */

 /dts-v1/;
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@ -4,7 +4,7 @@
 *
 * (C) Copyright 2014 - 2021, Xilinx, Inc.
 *
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as