arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board

Enable PCIe controller and PHY for sc7280 IDP board.
Add specific NVMe GPIO entries for SKU1 and SKU2 support.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1633628923-25047-4-git-send-email-pmaliset@codeaurora.org
This commit is contained in:
Prasad Malisetty 2021-10-07 23:18:41 +05:30 committed by Bjorn Andersson
parent 92e0ee9f83
commit 4e24d227aa
3 changed files with 66 additions and 0 deletions

View file

@ -65,6 +65,14 @@
status = "okay";
};
&nvme_pwren {
pins = "gpio19";
};
&nvme_3v3_regulator {
gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
};
&pmk8350_vadc {
pmr735a_die_temp {
reg = <PMR735A_ADC7_DIE_TEMP>;

View file

@ -31,6 +31,18 @@
linux,can-disable;
};
};
nvme_3v3_regulator: nvme-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "VLDO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&nvme_pwren>;
};
};
/*
@ -272,6 +284,23 @@
modem-init;
};
&pcie1 {
status = "okay";
perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
};
&pcie1_phy {
status = "okay";
vdda-phy-supply = <&vreg_l10c_0p8>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pmk8350_vadc {
pmk8350_die_temp {
reg = <PMK8350_ADC7_DIE_TEMP>;
@ -462,6 +491,27 @@
};
&tlmm {
nvme_pwren: nvme-pwren {
function = "gpio";
};
pcie1_reset_n: pcie1-reset-n {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
output-low;
bias-disable;
};
pcie1_wake_n: pcie1-wake-n {
pins = "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
qup_uart7_sleep_cts: qup-uart7-sleep-cts {
pins = "gpio28";
function = "gpio";

View file

@ -21,3 +21,11 @@
stdout-path = "serial0:115200n8";
};
};
&nvme_pwren {
pins = "gpio51";
};
&nvme_3v3_regulator {
gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
};