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soc: new SoC support for 6.17

Browse source 
These five newly supported chips come with both devicetree descriptions
 and the changes to wire them up to the build system for easier bisection.
 
 The chips in question are:
 
  - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
    in the product line that started with the Digital StrongARM SA1100
    based PDAs and continued with the Intel PXA2xx that dominated early
    smartphones. This one only made it only into a few products before the
    entire product line was cut in 2015.
 
  - The QiLai SoC is made by RISC-V core designer Andes Technologies
    and is in the 'Voyager' reference board in MicroATX form factor.
    It uses four in-order AX45MP cores, which is the midrange product
    from Andes.
 
  - CIX P1 is one of the few Arm chips designed for small workstations,
    and this one uses 12 Cortex-A720/A520 cores, making it also one
    of the only ARMv9.2 machines that one can but at the moment.
 
  - Axiado AX3000 is an embedded chip with relative small Cortex-A53
    CPU cores described as a "Trusted Control/Compute Unit" that can
    be used as a BMC in servers. In addition to the usual I/O, this one
    comes with 10GBit ethernet and and a 4TOPS NPU.
 
  - Sophgo SG2000 is an embedded chip that comes with both RISC-V
    and Arm cores that can run Linux. This was already supported for
    RISC-V but now it also works on Arm
 
 One more chip, the Black Sesame C1200 did not make it in tirm for the
 merge window.
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Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull new SoC support from Arnd Bergmann:
 "These five newly supported chips come with both devicetree
  descriptions and the changes to wire them up to the build system for
  easier bisection.

  The chips in question are:

   - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
     in the product line that started with the Digital StrongARM SA1100
     based PDAs and continued with the Intel PXA2xx that dominated early
     smartphones. This one only made it only into a few products before
     the entire product line was cut in 2015.

   - The QiLai SoC is made by RISC-V core designer Andes Technologies
     and is in the 'Voyager' reference board in MicroATX form factor. It
     uses four in-order AX45MP cores, which is the midrange product from
     Andes.

   - CIX P1 is one of the few Arm chips designed for small workstations,
     and this one uses 12 Cortex-A720/A520 cores, making it also one of
     the only ARMv9.2 machines that one can but at the moment.

   - Axiado AX3000 is an embedded chip with relative small Cortex-A53
     CPU cores described as a "Trusted Control/Compute Unit" that can be
     used as a BMC in servers. In addition to the usual I/O, this one
     comes with 10GBit ethernet and and a 4TOPS NPU.

   - Sophgo SG2000 is an embedded chip that comes with both RISC-V and
     Arm cores that can run Linux. This was already supported for RISC-V
     but now it also works on Arm

  One more chip, the Black Sesame C1200 did not make it in tirm for the
  merge window"

* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  arm64: defconfig: Enable rudimentary Sophgo SG2000 support
  arm64: Add SOPHGO SOC family Kconfig support
  arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
  arm64: dts: sophgo: Add Duo Module 01
  arm64: dts: sophgo: Add initial SG2000 SoC device tree
  MAINTAINERS: Add entry for Axiado
  arm64: defconfig: enable the Axiado family
  arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
  arm64: add Axiado SoC family
  dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
  dt-bindings: serial: cdns: add Axiado AX3000 UART controller
  dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
  dt-bindings: gpio: cdns: convert to YAML
  dt-bindings: arm: axiado: add AX3000 EVK compatible strings
  dt-bindings: vendor-prefixes: Add Axiado Corporation
  MAINTAINERS: Add CIX SoC maintainer entry
  arm64: dts: cix: Add sky1 base dts initial support
  dt-bindings: clock: cix: Add CIX sky1 scmi clock id
  arm64: defconfig: Enable CIX SoC
  mailbox: add CIX mailbox driver
  ...
This commit is contained in:
Linus Torvalds 2025-07-29 11:17:24 -07:00
commit 4df9c0a246
42 changed files with 3428 additions and 63 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
Documentation/devicetree/bindings/arm/axiado.yaml Normal file
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@ -0,0 +1,23 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/axiado.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axiado Platforms
maintainers:
- Harshit Shah <hshah@axiado.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: AX3000 based boards
items:
- enum:
- axiado,ax3000-evk # Axiado AX3000 Evaluation Board
- const: axiado,ax3000 # Axiado AX3000 SoC
additionalProperties: true

26
Documentation/devicetree/bindings/arm/cix.yaml Normal file
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@ -0,0 +1,26 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CIX platforms
maintainers:
- Peter Chen <peter.chen@cixtech.com>
- Fugang Duan <fugang.duan@cixtech.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Radxa Orion O6
items:
- const: radxa,orion-o6
- const: cix,sky1
additionalProperties: true
...

5
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
View file

@ -35,6 +35,11 @@ properties:
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
- description: PXA1908 based boards
items:
- enum:
- samsung,coreprimevelte
- const: marvell,pxa1908
additionalProperties: true

43
Documentation/devicetree/bindings/gpio/cdns,gpio.txt
View file

@ -1,43 +0,0 @@
Cadence GPIO controller bindings
Required properties:
- compatible: should be "cdns,gpio-r1p02".
- reg: the register base address and size.
- #gpio-cells: should be 2.
* first cell is the GPIO number.
* second cell specifies the GPIO flags, as defined in
<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW flags are supported.
- gpio-controller: marks the device as a GPIO controller.
- clocks: should contain one entry referencing the peripheral clock driving
the GPIO controller.
Optional properties:
- ngpios: integer number of gpio lines supported by this controller, up to 32.
- interrupts: interrupt specifier for the controllers interrupt.
- interrupt-controller: marks the device as an interrupt controller. When
defined, interrupts, interrupt-parent and #interrupt-cells
are required.
- interrupt-cells: should be 2.
* first cell is the GPIO number you want to use as an IRQ source.
* second cell specifies the IRQ type, as defined in
<dt-bindings/interrupt-controller/irq.h>.
Currently only level sensitive IRQs are supported.
Example:
gpio0: gpio-controller@fd060000 {
compatible = "cdns,gpio-r1p02";
reg =<0xfd060000 0x1000>;
clocks = <&gpio_clk>;
interrupt-parent = <&gic>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

84
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml Normal file
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@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence GPIO Controller
maintainers:
- Jan Kotas <jank@cadence.com>
properties:
compatible:
oneOf:
- const: cdns,gpio-r1p02
- items:
- enum:
- axiado,ax3000-gpio
- const: cdns,gpio-r1p02
reg:
maxItems: 1
clocks:
maxItems: 1
ngpios:
minimum: 1
maximum: 32
gpio-controller: true
"#gpio-cells":
const: 2
description: |
- First cell is the GPIO line number.
- Second cell is flags as defined in <dt-bindings/gpio/gpio.h>,
only GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW supported.
interrupt-controller: true
"#interrupt-cells":
const: 2
description: |
- First cell is the GPIO line number used as IRQ.
- Second cell is the trigger type, as defined in
<dt-bindings/interrupt-controller/irq.h>.
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- gpio-controller
- "#gpio-cells"
if:
required: [interrupt-controller]
then:
required:
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
gpio0: gpio-controller@fd060000 {
compatible = "cdns,gpio-r1p02";
reg = <0xfd060000 0x1000>;
clocks = <&gpio_clk>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

7
Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
View file

@ -14,7 +14,12 @@ allOf:
properties:
compatible:
const: cdns,i3c-master
oneOf:
- const: cdns,i3c-master
- items:
- enum:
- axiado,ax3000-i3c
- const: cdns,i3c-master
reg:
maxItems: 1

54
Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml Normal file
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andes machine-level software interrupt controller
description:
In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
second time with all interrupt sources tied to zero as the software interrupt
controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
generate machine-mode inter-processor interrupts through programming its
registers.
maintainers:
- Ben Zong-You Xie <ben717@andestech.com>
properties:
compatible:
items:
- enum:
- andestech,qilai-plicsw
- const: andestech,plicsw
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 15872
description:
Specifies which harts are connected to the PLIC_SW. Each item must points
to a riscv,cpu-intc node, which has a riscv cpu node as parent.
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
interrupt-controller@400000 {
compatible = "andestech,qilai-plicsw", "andestech,plicsw";
reg = <0x400000 0x400000>;
interrupts-extended = <&cpu0intc 3>,
<&cpu1intc 3>,
<&cpu2intc 3>,
<&cpu3intc 3>;
};

1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View file

@ -53,6 +53,7 @@ properties:
oneOf:
- items:
- enum:
- andestech,qilai-plic
- renesas,r9a07g043-plic
- const: andestech,nceplic100
- items:

77
Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml Normal file
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@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cixtech mailbox controller
maintainers:
- Guomin Chen <Guomin.Chen@cixtech.com>
description:
The Cixtech mailbox controller, used in the Cixtech Sky1 SoC,
is used for message transmission between multiple processors
within the SoC, such as the AP, PM, audio DSP, SensorHub MCU,
and others
Each Cixtech mailbox controller is unidirectional, so they are
typically used in pairs-one for receiving and one for transmitting.
Each Cixtech mailbox supports 11 channels with different transmission modes
channel 0-7 - Fast channel with 32bit transmit register and IRQ support
channel 8 - Doorbell mode,using the mailbox as an interrupt-generating
mechanism.
channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support
channel 10 - Reg based channel with 32*32bit transmit register and
Doorbell+transmit acknowledgment IRQ support
In the CIX Sky1 SoC use case, there are 4 pairs of mailbox controllers
AP <--> PM - using Doorbell transfer mode
AP <--> SE - using REG transfer mode
AP <--> DSP - using FIFO transfer mode
AP <--> SensorHub - using FIFO transfer mode
properties:
compatible:
const: cix,sky1-mbox
reg:
maxItems: 1
interrupts:
maxItems: 1
"#mbox-cells":
const: 1
cix,mbox-dir:
$ref: /schemas/types.yaml#/definitions/string
description: Direction of the mailbox relative to the AP
enum: [tx, rx]
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
- cix,mbox-dir
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
mbox_ap2pm: mailbox@30000000 {
compatible = "cix,sky1-mbox";
reg = <0 0x30000000 0 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
};

36
Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
View file

@ -30,6 +30,26 @@ allOf:
maxItems: 1
reg-names:
maxItems: 1
- if:
properties:
compatible:
contains:
const: mrvl,pxav1-mmc
then:
properties:
pinctrl-names:
description:
Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between
SDIO CMD and GPIO mode.
items:
- const: default
- const: state_cmd_gpio
pinctrl-0:
description:
Should contain default pinctrl.
pinctrl-1:
description:
Should switch CMD pin to GPIO mode as a high output.
properties:
compatible:
@ -62,22 +82,6 @@ properties:
- const: io
- const: core
pinctrl-names:
description:
Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between
SDIO CMD and GPIO mode.
items:
- const: default
- const: state_cmd_gpio
pinctrl-0:
description:
Should contain default pinctrl.
pinctrl-1:
description:
Should switch CMD pin to GPIO mode as a high output.
mrvl,clk-delay-cycles:
description: Specify a number of cycles to delay for tuning.
$ref: /schemas/types.yaml#/definitions/uint32

25
Documentation/devicetree/bindings/riscv/andes.yaml Normal file
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@ -0,0 +1,25 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/andes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andes SoC-based boards
maintainers:
- Ben Zong-You Xie <ben717@andestech.com>
description:
Andes SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- andestech,voyager
- const: andestech,qilai
additionalProperties: true

7
Documentation/devicetree/bindings/serial/cdns,uart.yaml
View file

@ -16,9 +16,10 @@ properties:
items:
- const: xlnx,xuartps
- const: cdns,uart-r1p8
- description: UART controller for Zynq Ultrascale+ MPSoC
items:
- const: xlnx,zynqmp-uart
- items:
- enum:
- axiado,ax3000-uart
- xlnx,zynqmp-uart
- const: cdns,uart-r1p12
reg:

53
Documentation/devicetree/bindings/timer/andestech,plmt0.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andes machine-level timer
description:
The Andes machine-level timer device (PLMT0) provides machine-level timer
functionality for a set of HARTs on a RISC-V platform. It has a single
fixed-frequency monotonic time counter (MTIME) register and a time compare
register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
generated if MTIME >= MTIMECMP.
maintainers:
- Ben Zong-You Xie <ben717@andestech.com>
properties:
compatible:
items:
- enum:
- andestech,qilai-plmt
- const: andestech,plmt0
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 32
description:
Specifies which harts are connected to the PLMT0. Each item must points
to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
PLMT0 supports 1 hart up to 32 harts.
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
interrupt-controller@100000 {
compatible = "andestech,qilai-plmt", "andestech,plmt0";
reg = <0x100000 0x100000>;
interrupts-extended = <&cpu0intc 7>,
<&cpu1intc 7>,
<&cpu2intc 7>,
<&cpu3intc 7>;
};

4
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file

@ -203,6 +203,8 @@ patternProperties:
description: Shanghai Awinic Technology Co., Ltd.
"^axentia,.*":
description: Axentia Technologies AB
"^axiado,.*":
description: Axiado Corporation
"^axis,.*":
description: Axis Communications AB
"^azoteq,.*":
@ -309,6 +311,8 @@ patternProperties:
description: Cirrus Logic, Inc.
"^cisco,.*":
description: Cisco Systems, Inc.
"^cix,.*":
description: CIX Technology Group Co., Ltd.
"^clockwork,.*":
description: Clockwork Tech LLC
"^cloos,.*":

38
MAINTAINERS
View file

@ -2449,6 +2449,14 @@ F: arch/arm/boot/dts/aspeed/
F: arch/arm/mach-aspeed/
N: aspeed
ARM/AXIADO ARCHITECTURE
M: Harshit Shah <hshah@axiado.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/axiado.yaml
F: arch/arm64/boot/dts/axiado/
N: axiado
ARM/AXM LSI SOC
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2508,6 +2516,19 @@ F: arch/arm/boot/compressed/misc-ep93xx.h
F: arch/arm/mach-ep93xx/
F: drivers/iio/adc/ep93xx_adc.c
ARM/CIX SOC SUPPORT
M: Peter Chen <peter.chen@cixtech.com>
M: Fugang Duan <fugang.duan@cixtech.com>
R: CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git
F: Documentation/devicetree/bindings/arm/cix.yaml
F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml
F: arch/arm64/boot/dts/cix/
F: drivers/mailbox/cix-mailbox.c
K: \bcix\b
ARM/CLKDEV SUPPORT
M: Russell King <linux@armlinux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2824,6 +2845,14 @@ F: drivers/irqchip/irq-mvebu-*
F: drivers/pinctrl/mvebu/
F: drivers/rtc/rtc-armada38x.c
ARM/Marvell PXA1908 SOC support
M: Duje Mihanović <duje@dujemihanovic.xyz>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/marvell/mmp/
F: drivers/clk/mmp/clk-pxa1908*.c
F: include/dt-bindings/clock/marvell,pxa1908.h
ARM/Mediatek RTC DRIVER
M: Eddie Huang <eddie.huang@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
@ -21379,6 +21408,15 @@ F: drivers/irqchip/irq-riscv-intc.c
F: include/linux/irqchip/riscv-aplic.h
F: include/linux/irqchip/riscv-imsic.h
RISC-V ANDES SoC Support
M: Ben Zong-You Xie <ben717@andestech.com>
S: Maintained
T: git: https://github.com/ben717-linux/linux
F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
F: Documentation/devicetree/bindings/riscv/andes.yaml
F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
F: arch/riscv/boot/dts/andes/
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>

26
arch/arm64/Kconfig.platforms
View file

@ -40,6 +40,12 @@ config ARCH_APPLE
This enables support for Apple's in-house ARM SoC family, such
as the Apple M1.
config ARCH_AXIADO
bool "Axiado SoC Family"
select GPIOLIB
help
This enables support for Axiado SoC family like AX3000
menuconfig ARCH_BCM
bool "Broadcom SoC Support"
@ -106,6 +112,12 @@ config ARCH_BLAIZE
help
This enables support for the Blaize SoC family
config ARCH_CIX
bool "Cixtech SoC family"
help
This enables support for the Cixtech SoC family,
like P1(sky1).
config ARCH_EXYNOS
bool "Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
@ -178,6 +190,14 @@ config ARCH_MESON
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
config ARCH_MMP
bool "Marvell MMP SoC Family"
select PINCTRL
select PINCTRL_SINGLE
help
This enables support for Marvell MMP SoC family, currently
supporting PXA1908 aka IAP140.
config ARCH_MVEBU
bool "Marvell EBU SoC Family"
select ARMADA_AP806_SYSCON
@ -307,6 +327,12 @@ config ARCH_INTEL_SOCFPGA
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
Agilex and eASIC N5X.
config ARCH_SOPHGO
bool "Sophgo SoCs"
select ARCH_HAS_RESET_CONTROLLER
help
This enables support for Sophgo SoC platform hardware.
config ARCH_STM32
bool "STMicroelectronics STM32 SoC Family"
select GPIOLIB

3
arch/arm64/boot/dts/Makefile
View file

@ -9,10 +9,12 @@ subdir-y += amlogic
subdir-y += apm
subdir-y += apple
subdir-y += arm
subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
subdir-y += cavium
subdir-y += cix
subdir-y += exynos
subdir-y += freescale
subdir-y += hisilicon
@ -28,6 +30,7 @@ subdir-y += realtek
subdir-y += renesas
subdir-y += rockchip
subdir-y += socionext
subdir-y += sophgo
subdir-y += sprd
subdir-y += st
subdir-y += synaptics

2
arch/arm64/boot/dts/axiado/Makefile Normal file
View file

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb

79
arch/arm64/boot/dts/axiado/ax3000-evk.dts Normal file
View file

@ -0,0 +1,79 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
*/
/dts-v1/;
#include "ax3000.dtsi"
/ {
model = "Axiado AX3000 EVK";
compatible = "axiado,ax3000-evk", "axiado,ax3000";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial3 = &uart3;
};
chosen {
stdout-path = "serial3:115200";
};
memory@0 {
device_type = "memory";
/* Cortex-A53 will use following memory map */
reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
<0x00000004 0x00000000 0x00000000 0x80000000>;
};
};
/* GPIO bank 0 - 7 */
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&gpio6 {
status = "okay";
};
&gpio7 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};

520
arch/arm64/boot/dts/axiado/ax3000.dtsi Normal file
View file

@ -0,0 +1,520 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
/ {
model = "Axiado AX3000";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x3c0013a0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x3c0013a0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x3c0013a0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x3c0013a0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-size = <0x100000>;
cache-unified;
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
};
};
clocks {
clk_xin: clock-200000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "clk_xin";
};
refclk: clock-125000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
soc {
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
gic500: interrupt-controller@80300000 {
compatible = "arm,gic-v3";
reg = <0x00 0x80300000 0x00 0x10000>,
<0x00 0x80380000 0x00 0x80000>;
ranges;
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
interrupt-controller;
#redistributor-regions = <1>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
/* GPIO Controller banks 0 - 7 */
gpio0: gpio-controller@80500000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80500000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@80580000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80580000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@80600000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80600000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@80680000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80680000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@80700000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80700000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@80780000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80780000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@80800000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80800000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@80880000 {
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
reg = <0x00 0x80880000 0x00 0x400>;
clocks = <&refclk>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
/* I3C Controller 0 - 16 */
i3c0: i3c@80500400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80500400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c1: i3c@80500800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80500800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c2: i3c@80580400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80580400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c3: i3c@80580800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80580800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c4: i3c@80600400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80600400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c5: i3c@80600800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80600800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c6: i3c@80680400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80680400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c7: i3c@80680800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80680800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c8: i3c@80700400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80700400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c9: i3c@80700800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80700800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c10: i3c@80780400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80780400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c11: i3c@80780800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80780800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c12: i3c@80800400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80800400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c13: i3c@80800800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80800800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c14: i3c@80880400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80880400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c15: i3c@80880800 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80880800 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
i3c16: i3c@80620400 {
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
reg = <0x00 0x80620400 0x00 0x400>;
clocks = <&refclk &clk_xin>;
clock-names = "pclk", "sysclk";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
i2c-scl-hz = <100000>;
i3c-scl-hz = <400000>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@80520000 {
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
reg = <0x00 0x80520000 0x00 0x100>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "uart_clk", "pclk";
clocks = <&refclk &refclk>;
status = "disabled";
};
uart1: serial@805a0000 {
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
reg = <0x00 0x805A0000 0x00 0x100>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "uart_clk", "pclk";
clocks = <&refclk &refclk>;
status = "disabled";
};
uart2: serial@80620000 {
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
reg = <0x00 0x80620000 0x00 0x100>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "uart_clk", "pclk";
clocks = <&refclk &refclk>;
status = "disabled";
};
uart3: serial@80520800 {
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
reg = <0x00 0x80520800 0x00 0x100>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "uart_clk", "pclk";
clocks = <&refclk &refclk>;
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic500>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
};

2
arch/arm64/boot/dts/cix/Makefile Normal file
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@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb

39
arch/arm64/boot/dts/cix/sky1-orion-o6.dts Normal file
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@ -0,0 +1,39 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright 2025 Cix Technology Group Co., Ltd.
*
*/
/dts-v1/;
#include "sky1.dtsi"
/ {
model = "Radxa Orion O6";
compatible = "radxa,orion-o6", "cix,sky1";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = &uart2;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x28000000>;
linux,cma-default;
};
};
};
&uart2 {
status = "okay";
};

330
arch/arm64/boot/dts/cix/sky1.dtsi Normal file
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@ -0,0 +1,330 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright 2025 Cix Technology Group Co., Ltd.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/cix,sky1.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x0>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x100>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu2: cpu@200 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x200>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu3: cpu@300 {
compatible = "arm,cortex-a520";
enable-method = "psci";
reg = <0x0 0x300>;
device_type = "cpu";
capacity-dmips-mhz = <403>;
};
cpu4: cpu@400 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x400>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu5: cpu@500 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x500>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu6: cpu@600 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x600>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu7: cpu@700 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x700>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu8: cpu@800 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x800>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu9: cpu@900 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0x900>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu10: cpu@a00 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0xa00>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu11: cpu@b00 {
compatible = "arm,cortex-a720";
enable-method = "psci";
reg = <0x0 0xb00>;
device_type = "cpu";
capacity-dmips-mhz = <1024>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
core6 {
cpu = <&cpu6>;
};
core7 {
cpu = <&cpu7>;
};
core8 {
cpu = <&cpu8>;
};
core9 {
cpu = <&cpu9>;
};
core10 {
cpu = <&cpu10>;
};
core11 {
cpu = <&cpu11>;
};
};
};
};
firmware {
ap_to_pm_scmi: scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>;
shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
};
pmu-a720 {
compatible = "arm,cortex-a720-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc@0 {
compatible = "simple-bus";
ranges = <0 0 0 0 0x20 0>;
dma-ranges;
#address-cells = <2>;
#size-cells = <2>;
uart0: serial@40b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040b0000 0x0 0x1000>;
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@40c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040c0000 0x0 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@40d0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040d0000 0x0 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: serial@40e0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x040e0000 0x0 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
mbox_ap2se: mailbox@5060000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x05060000 0x0 0x10000>;
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
mbox_se2ap: mailbox@5070000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x05070000 0x0 0x10000>;
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "rx";
};
ap2pm_scmi_mem: shmem@6590000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x06590000 0x0 0x80>;
reg-io-width = <4>;
};
mbox_ap2pm: mailbox@6590080 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x06590080 0x0 0xff80>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
pm2ap_scmi_mem: shmem@65a0000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x065a0000 0x0 0x80>;
reg-io-width = <4>;
};
mbox_pm2ap: mailbox@65a0080 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x065a0080 0x0 0xff80>;
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "rx";
};
mbox_sfh2ap: mailbox@8090000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x08090000 0x0 0x10000>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "rx";
};
mbox_ap2sfh: mailbox@80a0000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x080a0000 0x0 0x10000>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <1>;
cix,mbox-dir = "tx";
};
gic: interrupt-controller@e010000 {
compatible = "arm,gic-v3";
reg = <0x0 0x0e010000 0 0x10000>, /* GICD */
<0x0 0x0e090000 0 0x300000>; /* GICR * 12 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
#interrupt-cells = <4>;
interrupt-controller;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic_its: msi-controller@e050000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x0e050000 0x0 0x30000>;
msi-controller;
#msi-cells = <1>;
};
ppi-partitions {
ppi_partition0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_partition1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
};
};

2
arch/arm64/boot/dts/marvell/Makefile
View file

@ -32,3 +32,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
subdir-y += mmp

2
arch/arm64/boot/dts/marvell/mmp/Makefile Normal file
View file

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb

331
arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts Normal file
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@ -0,0 +1,331 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "pxa1908.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
model = "Samsung Galaxy Core Prime VE LTE";
compatible = "samsung,coreprimevelte", "marvell,pxa1908";
aliases {
mmc0 = &sdh2; /* eMMC */
mmc1 = &sdh0; /* SD card */
serial0 = &uart0;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0:115200n8";
fb0: framebuffer@17177000 {
compatible = "simple-framebuffer";
reg = <0 0x17177000 0 (480 * 800 * 4)>;
width = <480>;
height = <800>;
stride = <(480 * 4)>;
format = "a8r8g8b8";
};
};
/* Bootloader fills this in */
memory@0 {
device_type = "memory";
reg = <0 0 0 0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer@17000000 {
reg = <0 0x17000000 0 0x1800000>;
no-map;
};
gpu@9000000 {
reg = <0 0x9000000 0 0x1000000>;
};
/* Communications processor, aka modem */
cp@5000000 {
reg = <0 0x5000000 0 0x3000000>;
};
cm3@a000000 {
reg = <0 0xa000000 0 0x80000>;
};
seclog@8000000 {
reg = <0 0x8000000 0 0x100000>;
};
ramoops@8100000 {
compatible = "ramoops";
reg = <0 0x8100000 0 0x40000>;
record-size = <0x8000>;
console-size = <0x20000>;
max-reason = <5>;
};
};
i2c-muic {
compatible = "i2c-gpio";
sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <3>;
i2c-gpio,timeout-ms = <100>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c_muic_pins>;
muic: extcon@14 {
compatible = "siliconmitus,sm5504-muic";
reg = <0x14>;
interrupt-parent = <&gpio>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins>;
autorepeat;
key-home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
};
key-volup {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
key-voldown {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
};
};
&smmu {
status = "okay";
};
&pmx {
pinctrl-single,gpio-range = <&range 55 55 0>,
<&range 110 32 0>,
<&range 52 1 0>;
pinctrl-names = "default";
pinctrl-0 = <&board_pins_0 &board_pins_1 &board_pins_2>;
board_pins_0: board-pins-0 {
pinctrl-single,pins = <
0x160 0
0x164 0
0x168 0
0x16c 0
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0x288 0x388>;
};
board_pins_1: board-pins-1 {
pinctrl-single,pins = <
0x44 1
0x48 1
0x20 1
0x18 1
0x14 1
0x10 1
0xc 1
0x8 1
0x68 1
0x58 0
0x54 0
0x7c 0
0x6c 0
0x70 0
0x4c 1
0x50 1
0xac 0
0x90 0
0x8c 0
0x88 0
0x84 0
0xc8 0
0x128 0
0x190 0
0x194 0
0x1a0 0
0x114 0
0x118 0
0x1d8 0
0x1e4 0
0xe8 0
0x100 0
0x204 0
0x210 0
0x218 0
>;
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
pinctrl-single,low-power-mode = <0x288 0x388>;
};
board_pins_2: board-pins-2 {
pinctrl-single,pins = <
0x260 0
0x264 0
0x268 0
0x26c 0
0x270 0
0x274 0
0x78 0
0x74 0
0xb0 1
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0 0x388>;
};
uart0_pins: uart0-pins {
pinctrl-single,pins = <
0x198 6
0x19c 6
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0 0x388>;
};
gpio_keys_pins: gpio-keys-pins {
pinctrl-single,pins = <
0x11c 0
0x120 0
0x1a4 0
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0 0x388>;
};
i2c_muic_pins: i2c-muic-pins {
pinctrl-single,pins = <
0x154 0
0x150 0
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0x288 0x388>;
};
sdh0_pins_0: sdh0-pins-0 {
pinctrl-single,pins = <
0x108 0
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0 0x388>;
};
sdh0_pins_1: sdh0-pins-1 {
pinctrl-single,pins = <
0x94 0
0x98 0
0x9c 0
0xa0 0
0xa4 0
>;
pinctrl-single,drive-strength = <0x800 0x1800>;
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0 0x388>;
};
sdh0_pins_2: sdh0-pins-2 {
pinctrl-single,pins = <
0xa8 0
>;
pinctrl-single,drive-strength = <0x1000 0x1800>;
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
pinctrl-single,input-schmitt = <0 0x30>;
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
pinctrl-single,low-power-mode = <0x208 0x388>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&twsi0 {
status = "okay";
};
&twsi1 {
status = "okay";
};
&twsi2 {
status = "okay";
};
&twsi3 {
status = "okay";
};
&usb {
extcon = <&muic>, <&muic>;
};
&sdh2 {
/* Disabled for now because initialization fails with -ETIMEDOUT. */
status = "disabled";
bus-width = <8>;
non-removable;
mmc-ddr-1_8v;
};
&sdh0 {
pinctrl-names = "default";
pinctrl-0 = <&sdh0_pins_0 &sdh0_pins_1 &sdh0_pins_2>;
cd-gpios = <&gpio 11 0>;
cd-inverted;
bus-width = <4>;
wp-inverted;
};

300
arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi Normal file
View file

@ -0,0 +1,300 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/marvell,pxa1908.h>
/ {
model = "Marvell Armada PXA1908";
compatible = "marvell,pxa1908";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 3>;
enable-method = "psci";
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
smmu: iommu@c0010000 {
compatible = "arm,mmu-400";
reg = <0 0xc0010000 0 0x10000>;
#global-interrupts = <1>;
#iommu-cells = <1>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gic: interrupt-controller@d1df9000 {
compatible = "arm,gic-400";
reg = <0 0xd1df9000 0 0x1000>,
<0 0xd1dfa000 0 0x2000>,
/* The subsequent registers are guesses. */
<0 0xd1dfc000 0 0x2000>,
<0 0xd1dfe000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
apb@d4000000 {
compatible = "simple-bus";
reg = <0 0xd4000000 0 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xd4000000 0x200000>;
pdma: dma-controller@0 {
compatible = "marvell,pdma-1.0";
reg = <0 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <30>;
#dma-cells = <2>;
};
twsi1: i2c@10800 {
compatible = "mrvl,mmp-twsi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10800 0x64>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbc PXA1908_CLK_TWSI1>;
mrvl,i2c-fast-mode;
status = "disabled";
};
twsi0: i2c@11000 {
compatible = "mrvl,mmp-twsi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11000 0x64>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbc PXA1908_CLK_TWSI0>;
mrvl,i2c-fast-mode;
status = "disabled";
};
twsi3: i2c@13800 {
compatible = "mrvl,mmp-twsi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x13800 0x64>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbc PXA1908_CLK_TWSI3>;
mrvl,i2c-fast-mode;
status = "disabled";
};
apbc: clock-controller@15000 {
compatible = "marvell,pxa1908-apbc";
reg = <0x15000 0x1000>;
#clock-cells = <1>;
};
uart0: serial@17000 {
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0x17000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbc PXA1908_CLK_UART0>;
reg-shift = <2>;
};
uart1: serial@18000 {
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0x18000 0x1000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbc PXA1908_CLK_UART1>;
reg-shift = <2>;
};
gpio: gpio@19000 {
compatible = "marvell,mmp-gpio";
reg = <0x19000 0x800>;
#address-cells = <1>;
#size-cells = <1>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&apbc PXA1908_CLK_GPIO>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpio_mux";
interrupt-controller;
#interrupt-cells = <2>;
ranges = <0 0x19000 0x800>;
gpio@0 {
reg = <0x0 0x4>;
};
gpio@4 {
reg = <0x4 0x4>;
};
gpio@8 {
reg = <0x8 0x4>;
};
gpio@100 {
reg = <0x100 0x4>;
};
};
pmx: pinmux@1e000 {
compatible = "marvell,pxa1908-padconf", "pinconf-single";
reg = <0x1e000 0x330>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
uart2: serial@36000 {
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0x36000 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbcp PXA1908_CLK_UART2>;
reg-shift = <2>;
};
twsi2: i2c@37000 {
compatible = "mrvl,mmp-twsi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x37000 0x64>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbcp PXA1908_CLK_TWSI2>;
mrvl,i2c-fast-mode;
status = "disabled";
};
apbcp: clock-controller@3b000 {
compatible = "marvell,pxa1908-apbcp";
reg = <0x3b000 0x1000>;
#clock-cells = <1>;
};
mpmu: clock-controller@50000 {
compatible = "marvell,pxa1908-mpmu";
reg = <0x50000 0x1000>;
#clock-cells = <1>;
};
};
axi@d4200000 {
compatible = "simple-bus";
reg = <0 0xd4200000 0 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xd4200000 0x200000>;
usbphy: phy@7000 {
compatible = "marvell,pxa1928-usb-phy";
reg = <0x7000 0x200>;
clocks = <&apmu PXA1908_CLK_USB>;
#phy-cells = <0>;
};
usb: usb@8000 {
compatible = "chipidea,usb2";
reg = <0x8000 0x200>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apmu PXA1908_CLK_USB>;
phys = <&usbphy>;
phy-names = "usb-phy";
};
sdh0: mmc@80000 {
compatible = "mrvl,pxav3-mmc";
reg = <0x80000 0x120>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apmu PXA1908_CLK_SDH0>;
clock-names = "io";
mrvl,clk-delay-cycles = <31>;
};
sdh1: mmc@80800 {
compatible = "mrvl,pxav3-mmc";
reg = <0x80800 0x120>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apmu PXA1908_CLK_SDH1>;
clock-names = "io";
mrvl,clk-delay-cycles = <31>;
};
sdh2: mmc@81000 {
compatible = "mrvl,pxav3-mmc";
reg = <0x81000 0x120>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apmu PXA1908_CLK_SDH2>;
clock-names = "io";
mrvl,clk-delay-cycles = <31>;
};
apmu: clock-controller@82800 {
compatible = "marvell,pxa1908-apmu";
reg = <0x82800 0x400>;
#clock-cells = <1>;
};
};
};
};

2
arch/arm64/boot/dts/sophgo/Makefile Normal file
View file

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-module-01-evb.dtb

76
arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts Normal file
View file

@ -0,0 +1,76 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "sg2000-milkv-duo-module-01.dtsi"
/ {
model = "Milk-V Duo Module 01 Evaluation Board";
compatible = "milkv,duo-module-01-evb", "milkv,duo-module-01", "sophgo,sg2000";
chosen {
stdout-path = "serial0:115200n8";
};
};
&pinctrl {
sdhci0_cfg: sdhci0-cfg {
sdhci0-cd-pins {
pinmux = <PINMUX(PIN_SD0_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-clk-pins {
pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
bias-pull-up;
drive-strength-microamp = <16100>;
power-source = <3300>;
};
sdhci0-cmd-pins {
pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-data-pins {
pinmux = <PINMUX(PIN_SD0_D0, 0)>,
<PINMUX(PIN_SD0_D1, 0)>,
<PINMUX(PIN_SD0_D2, 0)>,
<PINMUX(PIN_SD0_D3, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};
&sdhci0 {
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
pinctrl-0 = <&sdhci0_cfg>;
pinctrl-names = "default";
status = "okay";
};

40
arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi Normal file
View file

@ -0,0 +1,40 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
#include "sg2000.dtsi"
/ {
model = "Milk-V Duo Module 01";
compatible = "milkv,duo-module-01", "sophgo,sg2000";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
};
&osc {
clock-frequency = <25000000>;
};
&emmc {
bus-width = <4>;
no-1-8-v;
cap-mmc-hw-reset;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
/* Wi-Fi */
&sdhci1 {
bus-width = <4>;
cap-sdio-irq;
no-mmc;
no-sd;
non-removable;
};

86
arch/arm64/boot/dts/sophgo/sg2000.dtsi Normal file
View file

@ -0,0 +1,86 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <riscv/sophgo/cv180x.dtsi>
#include <riscv/sophgo/cv181x.dtsi>
/ {
compatible = "sophgo,sg2000";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
i-cache-size = <32768>;
d-cache-size = <32768>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x20000>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_on = <0xc4000003>;
cpu_off = <0x84000002>;
};
soc {
gic: interrupt-controller@1f01000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x01f01000 0x1000>,
<0x01f02000 0x2000>;
};
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2000-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,sg2000-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
clock-frequency = <25000000>;
};
};

7
arch/arm64/configs/defconfig
View file

@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
CONFIG_ARCH_APPLE=y
CONFIG_ARCH_AXIADO=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_BCM_IPROC=y
@ -45,6 +46,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_BLAIZE=y
CONFIG_ARCH_CIX=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
@ -66,6 +68,7 @@ CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_SOPHGO=y
CONFIG_ARCH_STM32=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
@ -655,6 +658,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=m
CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
CONFIG_PINCTRL_SM8550_LPASS_LPI=m
CONFIG_PINCTRL_SM8650_LPASS_LPI=m
CONFIG_PINCTRL_SOPHGO_SG2000=y
CONFIG_GPIO_ALTERA=m
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_DWAPB=y
@ -1432,6 +1436,7 @@ CONFIG_QCOM_HFPLL=y
CONFIG_CLK_GFM_LPASS_SM8250=m
CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
CONFIG_CLK_RENESAS_VBATTB=m
CONFIG_CLK_SOPHGO_CV1800=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_OMAP=m
CONFIG_HWSPINLOCK_QCOM=y
@ -1448,6 +1453,7 @@ CONFIG_QCOM_APCS_IPC=y
CONFIG_MTK_ADSP_MBOX=m
CONFIG_QCOM_CPUCP_MBOX=m
CONFIG_QCOM_IPCC=y
CONFIG_CIX_MBOX=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y
@ -1534,6 +1540,7 @@ CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=m
CONFIG_RZG2L_ADC=m
CONFIG_SOPHGO_CV1800B_ADC=m
CONFIG_TI_ADS1015=m
CONFIG_TI_AM335X_ADC=m
CONFIG_IIO_CROS_EC_SENSORS_CORE=m

7
arch/riscv/Kconfig.socs
View file

@ -1,5 +1,12 @@
menu "SoC selection"
config ARCH_ANDES
bool "Andes SoCs"
depends on MMU && !XIP_KERNEL
select ERRATA_ANDES
help
This enables support for Andes SoC platform hardware.
config ARCH_MICROCHIP_POLARFIRE
def_bool ARCH_MICROCHIP

1
arch/riscv/boot/dts/Makefile
View file

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += andes
subdir-y += canaan
subdir-y += microchip
subdir-y += renesas

2
arch/riscv/boot/dts/andes/Makefile Normal file
View file

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ANDES) += qilai-voyager.dtb

28
arch/riscv/boot/dts/andes/qilai-voyager.dts Normal file
View file

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
*/
#include "qilai.dtsi"
/ {
model = "Voyager";
compatible = "andestech,voyager", "andestech,qilai";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@400000000 {
device_type = "memory";
reg = <0x4 0x00000000 0x4 0x00000000>;
};
};
&uart0 {
status = "okay";
};

186
arch/riscv/boot/dts/andes/qilai.dtsi Normal file
View file

@ -0,0 +1,186 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <62500000>;
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
"zihpm", "xandespmu";
mmu-type = "riscv,sv39";
clock-frequency = <100000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-line-size = <64>;
next-level-cache = <&l2_cache>;
cpu0_intc: interrupt-controller {
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "andestech,ax45mp", "riscv";
device_type = "cpu";
reg = <1>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
"zihpm", "xandespmu";
mmu-type = "riscv,sv39";
clock-frequency = <100000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-line-size = <64>;
next-level-cache = <&l2_cache>;
cpu1_intc: interrupt-controller {
compatible = "andestech,cpu-intc",
"riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "andestech,ax45mp", "riscv";
device_type = "cpu";
reg = <2>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
"zihpm", "xandespmu";
mmu-type = "riscv,sv39";
clock-frequency = <100000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-line-size = <64>;
next-level-cache = <&l2_cache>;
cpu2_intc: interrupt-controller {
compatible = "andestech,cpu-intc",
"riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "andestech,ax45mp", "riscv";
device_type = "cpu";
reg = <3>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
"zihpm", "xandespmu";
mmu-type = "riscv,sv39";
clock-frequency = <100000000>;
i-cache-size = <0x8000>;
i-cache-sets = <256>;
i-cache-line-size = <64>;
d-cache-size = <0x8000>;
d-cache-sets = <128>;
d-cache-line-size = <64>;
next-level-cache = <&l2_cache>;
cpu3_intc: interrupt-controller {
compatible = "andestech,cpu-intc",
"riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
soc {
compatible = "simple-bus";
ranges;
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
plmt: timer@100000 {
compatible = "andestech,qilai-plmt", "andestech,plmt0";
reg = <0x0 0x00100000 0x0 0x100000>;
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
l2_cache: cache-controller@200000 {
compatible = "andestech,qilai-ax45mp-cache",
"andestech,ax45mp-cache", "cache";
reg = <0x0 0x00200000 0x0 0x100000>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
cache-line-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <0x200000>;
cache-unified;
};
plic_sw: interrupt-controller@400000 {
compatible = "andestech,qilai-plicsw",
"andestech,plicsw";
reg = <0x0 0x00400000 0x0 0x400000>;
interrupts-extended = <&cpu0_intc 3>,
<&cpu1_intc 3>,
<&cpu2_intc 3>,
<&cpu3_intc 3>;
};
plic: interrupt-controller@2000000 {
compatible = "andestech,qilai-plic",
"andestech,nceplic100";
reg = <0x0 0x02000000 0x0 0x2000000>;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>;
riscv,ndev = <71>;
};
uart0: serial@30300000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x0 0x30300000 0x0 0x100000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <50000000>;
reg-offset = <32>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test;
};
};
};

1
arch/riscv/configs/defconfig
View file

@ -22,6 +22,7 @@ CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_ARCH_ANDES=y
CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y

10
drivers/mailbox/Kconfig
View file

@ -340,4 +340,14 @@ config THEAD_TH1520_MBOX
kernel is running, and E902 core used for power management among other
things.
config CIX_MBOX
tristate "CIX Mailbox"
depends on ARCH_CIX || COMPILE_TEST
depends on OF
help
Mailbox implementation for CIX IPC system. The controller supports
11 mailbox channels with different operating mode and every channel
is unidirectional. Say Y here if you want to use the CIX Mailbox
support.
endif

2
drivers/mailbox/Makefile
View file

@ -72,3 +72,5 @@ obj-$(CONFIG_QCOM_CPUCP_MBOX) += qcom-cpucp-mbox.o
obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o
obj-$(CONFIG_THEAD_TH1520_MBOX) += mailbox-th1520.o
obj-$(CONFIG_CIX_MBOX) += cix-mailbox.o

645
drivers/mailbox/cix-mailbox.c Normal file
View file

@ -0,0 +1,645 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2025 Cix Technology Group Co., Ltd.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "mailbox.h"
/*
* The maximum transmission size is 32 words or 128 bytes.
*/
#define CIX_MBOX_MSG_WORDS 32 /* Max length = 32 words */
#define CIX_MBOX_MSG_LEN_MASK 0x7fL /* Max length = 128 bytes */
/* [0~7] Fast channel
* [8] doorbell base channel
* [9]fifo base channel
* [10] register base channel
*/
#define CIX_MBOX_FAST_IDX 7
#define CIX_MBOX_DB_IDX 8
#define CIX_MBOX_FIFO_IDX 9
#define CIX_MBOX_REG_IDX 10
#define CIX_MBOX_CHANS 11
/* Register define */
#define CIX_REG_MSG(n) (0x0 + 0x4*(n)) /* 0x0~0x7c */
#define CIX_REG_DB_ACK CIX_REG_MSG(CIX_MBOX_MSG_WORDS) /* 0x80 */
#define CIX_ERR_COMP (CIX_REG_DB_ACK + 0x4) /* 0x84 */
#define CIX_ERR_COMP_CLR (CIX_REG_DB_ACK + 0x8) /* 0x88 */
#define CIX_REG_F_INT(IDX) (CIX_ERR_COMP_CLR + 0x4*(IDX+1)) /* 0x8c~0xa8 */
#define CIX_FIFO_WR (CIX_REG_F_INT(CIX_MBOX_FAST_IDX+1)) /* 0xac */
#define CIX_FIFO_RD (CIX_FIFO_WR + 0x4) /* 0xb0 */
#define CIX_FIFO_STAS (CIX_FIFO_WR + 0x8) /* 0xb4 */
#define CIX_FIFO_WM (CIX_FIFO_WR + 0xc) /* 0xb8 */
#define CIX_INT_ENABLE (CIX_FIFO_WR + 0x10) /* 0xbc */
#define CIX_INT_ENABLE_SIDE_B (CIX_FIFO_WR + 0x14) /* 0xc0 */
#define CIX_INT_CLEAR (CIX_FIFO_WR + 0x18) /* 0xc4 */
#define CIX_INT_STATUS (CIX_FIFO_WR + 0x1c) /* 0xc8 */
#define CIX_FIFO_RST (CIX_FIFO_WR + 0x20) /* 0xcc */
#define CIX_MBOX_TX 0
#define CIX_MBOX_RX 1
#define CIX_DB_INT_BIT BIT(0)
#define CIX_DB_ACK_INT_BIT BIT(1)
#define CIX_FIFO_WM_DEFAULT CIX_MBOX_MSG_WORDS
#define CIX_FIFO_STAS_WMK BIT(0)
#define CIX_FIFO_STAS_FULL BIT(1)
#define CIX_FIFO_STAS_EMPTY BIT(2)
#define CIX_FIFO_STAS_UFLOW BIT(3)
#define CIX_FIFO_STAS_OFLOW BIT(4)
#define CIX_FIFO_RST_BIT BIT(0)
#define CIX_DB_INT BIT(0)
#define CIX_ACK_INT BIT(1)
#define CIX_FIFO_FULL_INT BIT(2)
#define CIX_FIFO_EMPTY_INT BIT(3)
#define CIX_FIFO_WM01_INT BIT(4)
#define CIX_FIFO_WM10_INT BIT(5)
#define CIX_FIFO_OFLOW_INT BIT(6)
#define CIX_FIFO_UFLOW_INT BIT(7)
#define CIX_FIFO_N_EMPTY_INT BIT(8)
#define CIX_FAST_CH_INT(IDX) BIT((IDX)+9)
#define CIX_SHMEM_OFFSET 0x80
enum cix_mbox_chan_type {
CIX_MBOX_TYPE_DB,
CIX_MBOX_TYPE_REG,
CIX_MBOX_TYPE_FIFO,
CIX_MBOX_TYPE_FAST,
};
struct cix_mbox_con_priv {
enum cix_mbox_chan_type type;
struct mbox_chan *chan;
int index;
};
struct cix_mbox_priv {
struct device *dev;
int irq;
int dir;
void __iomem *base; /* region for mailbox */
struct cix_mbox_con_priv con_priv[CIX_MBOX_CHANS];
struct mbox_chan mbox_chans[CIX_MBOX_CHANS];
struct mbox_controller mbox;
bool use_shmem;
};
/*
* The CIX mailbox supports four types of transfers:
* CIX_MBOX_TYPE_DB, CIX_MBOX_TYPE_FAST, CIX_MBOX_TYPE_REG, and CIX_MBOX_TYPE_FIFO.
* For the REG and FIFO types of transfers, the message format is as follows:
*/
union cix_mbox_msg_reg_fifo {
u32 length; /* unit is byte */
u32 buf[CIX_MBOX_MSG_WORDS]; /* buf[0] must be the byte length of this array */
};
static struct cix_mbox_priv *to_cix_mbox_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct cix_mbox_priv, mbox);
}
static void cix_mbox_write(struct cix_mbox_priv *priv, u32 val, u32 offset)
{
if (priv->use_shmem)
iowrite32(val, priv->base + offset - CIX_SHMEM_OFFSET);
else
iowrite32(val, priv->base + offset);
}
static u32 cix_mbox_read(struct cix_mbox_priv *priv, u32 offset)
{
if (priv->use_shmem)
return ioread32(priv->base + offset - CIX_SHMEM_OFFSET);
else
return ioread32(priv->base + offset);
}
static bool mbox_fifo_empty(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
return ((cix_mbox_read(priv, CIX_FIFO_STAS) & CIX_FIFO_STAS_EMPTY) ? true : false);
}
/*
*The transmission unit of the CIX mailbox is word.
*The byte length should be converted into the word length.
*/
static inline u32 mbox_get_msg_size(void *msg)
{
u32 len;
len = ((u32 *)msg)[0] & CIX_MBOX_MSG_LEN_MASK;
return DIV_ROUND_UP(len, 4);
}
static int cix_mbox_send_data_db(struct mbox_chan *chan, void *data)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
/* trigger doorbell irq */
cix_mbox_write(priv, CIX_DB_INT_BIT, CIX_REG_DB_ACK);
return 0;
}
static int cix_mbox_send_data_reg(struct mbox_chan *chan, void *data)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
union cix_mbox_msg_reg_fifo *msg = data;
u32 len, i;
if (!data)
return -EINVAL;
len = mbox_get_msg_size(data);
for (i = 0; i < len; i++)
cix_mbox_write(priv, msg->buf[i], CIX_REG_MSG(i));
/* trigger doorbell irq */
cix_mbox_write(priv, CIX_DB_INT_BIT, CIX_REG_DB_ACK);
return 0;
}
static int cix_mbox_send_data_fifo(struct mbox_chan *chan, void *data)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
union cix_mbox_msg_reg_fifo *msg = data;
u32 len, val, i;
if (!data)
return -EINVAL;
len = mbox_get_msg_size(data);
cix_mbox_write(priv, len, CIX_FIFO_WM);
for (i = 0; i < len; i++)
cix_mbox_write(priv, msg->buf[i], CIX_FIFO_WR);
/* Enable fifo empty interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE);
val |= CIX_FIFO_EMPTY_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE);
return 0;
}
static int cix_mbox_send_data_fast(struct mbox_chan *chan, void *data)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
struct cix_mbox_con_priv *cp = chan->con_priv;
u32 *arg = (u32 *)data;
int index = cp->index;
if (!data)
return -EINVAL;
if (index < 0 || index > CIX_MBOX_FAST_IDX) {
dev_err(priv->dev, "Invalid Mbox index %d\n", index);
return -EINVAL;
}
cix_mbox_write(priv, arg[0], CIX_REG_F_INT(index));
return 0;
}
static int cix_mbox_send_data(struct mbox_chan *chan, void *data)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
struct cix_mbox_con_priv *cp = chan->con_priv;
if (priv->dir != CIX_MBOX_TX) {
dev_err(priv->dev, "Invalid Mbox dir %d\n", priv->dir);
return -EINVAL;
}
switch (cp->type) {
case CIX_MBOX_TYPE_DB:
cix_mbox_send_data_db(chan, data);
break;
case CIX_MBOX_TYPE_REG:
cix_mbox_send_data_reg(chan, data);
break;
case CIX_MBOX_TYPE_FIFO:
cix_mbox_send_data_fifo(chan, data);
break;
case CIX_MBOX_TYPE_FAST:
cix_mbox_send_data_fast(chan, data);
break;
default:
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
return -EINVAL;
}
return 0;
}
static void cix_mbox_isr_db(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
u32 int_status;
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
if (priv->dir == CIX_MBOX_RX) {
/* rx interrupt is triggered */
if (int_status & CIX_DB_INT) {
cix_mbox_write(priv, CIX_DB_INT, CIX_INT_CLEAR);
mbox_chan_received_data(chan, NULL);
/* trigger ack interrupt */
cix_mbox_write(priv, CIX_DB_ACK_INT_BIT, CIX_REG_DB_ACK);
}
} else {
/* tx ack interrupt is triggered */
if (int_status & CIX_ACK_INT) {
cix_mbox_write(priv, CIX_ACK_INT, CIX_INT_CLEAR);
mbox_chan_received_data(chan, NULL);
}
}
}
static void cix_mbox_isr_reg(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
u32 int_status;
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
if (priv->dir == CIX_MBOX_RX) {
/* rx interrupt is triggered */
if (int_status & CIX_DB_INT) {
u32 data[CIX_MBOX_MSG_WORDS], len, i;
cix_mbox_write(priv, CIX_DB_INT, CIX_INT_CLEAR);
data[0] = cix_mbox_read(priv, CIX_REG_MSG(0));
len = mbox_get_msg_size(data);
for (i = 1; i < len; i++)
data[i] = cix_mbox_read(priv, CIX_REG_MSG(i));
/* trigger ack interrupt */
cix_mbox_write(priv, CIX_DB_ACK_INT_BIT, CIX_REG_DB_ACK);
mbox_chan_received_data(chan, data);
}
} else {
/* tx ack interrupt is triggered */
if (int_status & CIX_ACK_INT) {
cix_mbox_write(priv, CIX_ACK_INT, CIX_INT_CLEAR);
mbox_chan_txdone(chan, 0);
}
}
}
static void cix_mbox_isr_fifo(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
u32 int_status, status;
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
if (priv->dir == CIX_MBOX_RX) {
/* FIFO waterMark interrupt is generated */
if (int_status & (CIX_FIFO_FULL_INT | CIX_FIFO_WM01_INT)) {
u32 data[CIX_MBOX_MSG_WORDS] = { 0 }, i = 0;
cix_mbox_write(priv, (CIX_FIFO_FULL_INT | CIX_FIFO_WM01_INT),
CIX_INT_CLEAR);
do {
data[i++] = cix_mbox_read(priv, CIX_FIFO_RD);
} while (!mbox_fifo_empty(chan) && i < CIX_MBOX_MSG_WORDS);
mbox_chan_received_data(chan, data);
}
/* FIFO underflow is generated */
if (int_status & CIX_FIFO_UFLOW_INT) {
status = cix_mbox_read(priv, CIX_FIFO_STAS);
dev_err(priv->dev, "fifo underflow: int_stats %d\n", status);
cix_mbox_write(priv, CIX_FIFO_UFLOW_INT, CIX_INT_CLEAR);
}
} else {
/* FIFO empty interrupt is generated */
if (int_status & CIX_FIFO_EMPTY_INT) {
u32 val;
cix_mbox_write(priv, CIX_FIFO_EMPTY_INT, CIX_INT_CLEAR);
/* Disable empty irq*/
val = cix_mbox_read(priv, CIX_INT_ENABLE);
val &= ~CIX_FIFO_EMPTY_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE);
mbox_chan_txdone(chan, 0);
}
/* FIFO overflow is generated */
if (int_status & CIX_FIFO_OFLOW_INT) {
status = cix_mbox_read(priv, CIX_FIFO_STAS);
dev_err(priv->dev, "fifo overlow: int_stats %d\n", status);
cix_mbox_write(priv, CIX_FIFO_OFLOW_INT, CIX_INT_CLEAR);
}
}
}
static void cix_mbox_isr_fast(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
struct cix_mbox_con_priv *cp = chan->con_priv;
u32 int_status, data;
/* no irq will be trigger for TX dir mbox */
if (priv->dir != CIX_MBOX_RX)
return;
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
if (int_status & CIX_FAST_CH_INT(cp->index)) {
cix_mbox_write(priv, CIX_FAST_CH_INT(cp->index), CIX_INT_CLEAR);
data = cix_mbox_read(priv, CIX_REG_F_INT(cp->index));
mbox_chan_received_data(chan, &data);
}
}
static irqreturn_t cix_mbox_isr(int irq, void *arg)
{
struct mbox_chan *chan = arg;
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
struct cix_mbox_con_priv *cp = chan->con_priv;
switch (cp->type) {
case CIX_MBOX_TYPE_DB:
cix_mbox_isr_db(chan);
break;
case CIX_MBOX_TYPE_REG:
cix_mbox_isr_reg(chan);
break;
case CIX_MBOX_TYPE_FIFO:
cix_mbox_isr_fifo(chan);
break;
case CIX_MBOX_TYPE_FAST:
cix_mbox_isr_fast(chan);
break;
default:
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int cix_mbox_startup(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
struct cix_mbox_con_priv *cp = chan->con_priv;
int index = cp->index, ret;
u32 val;
ret = request_irq(priv->irq, cix_mbox_isr, 0,
dev_name(priv->dev), chan);
if (ret) {
dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq);
return ret;
}
switch (cp->type) {
case CIX_MBOX_TYPE_DB:
/* Overwrite txdone_method for DB channel */
chan->txdone_method = TXDONE_BY_ACK;
fallthrough;
case CIX_MBOX_TYPE_REG:
if (priv->dir == CIX_MBOX_TX) {
/* Enable ACK interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE);
val |= CIX_ACK_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE);
} else {
/* Enable Doorbell interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
val |= CIX_DB_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
}
break;
case CIX_MBOX_TYPE_FIFO:
/* reset fifo */
cix_mbox_write(priv, CIX_FIFO_RST_BIT, CIX_FIFO_RST);
/* set default watermark */
cix_mbox_write(priv, CIX_FIFO_WM_DEFAULT, CIX_FIFO_WM);
if (priv->dir == CIX_MBOX_TX) {
/* Enable fifo overflow interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE);
val |= CIX_FIFO_OFLOW_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE);
} else {
/* Enable fifo full/underflow interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
val |= CIX_FIFO_UFLOW_INT|CIX_FIFO_WM01_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
}
break;
case CIX_MBOX_TYPE_FAST:
/* Only RX channel has intterupt */
if (priv->dir == CIX_MBOX_RX) {
if (index < 0 || index > CIX_MBOX_FAST_IDX) {
dev_err(priv->dev, "Invalid index %d\n", index);
ret = -EINVAL;
goto failed;
}
/* enable fast channel interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
val |= CIX_FAST_CH_INT(index);
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
}
break;
default:
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
ret = -EINVAL;
goto failed;
}
return 0;
failed:
free_irq(priv->irq, chan);
return ret;
}
static void cix_mbox_shutdown(struct mbox_chan *chan)
{
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
struct cix_mbox_con_priv *cp = chan->con_priv;
int index = cp->index;
u32 val;
switch (cp->type) {
case CIX_MBOX_TYPE_DB:
case CIX_MBOX_TYPE_REG:
if (priv->dir == CIX_MBOX_TX) {
/* Disable ACK interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE);
val &= ~CIX_ACK_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE);
} else if (priv->dir == CIX_MBOX_RX) {
/* Disable Doorbell interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
val &= ~CIX_DB_INT;
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
}
break;
case CIX_MBOX_TYPE_FIFO:
if (priv->dir == CIX_MBOX_TX) {
/* Disable empty/fifo overflow irq*/
val = cix_mbox_read(priv, CIX_INT_ENABLE);
val &= ~(CIX_FIFO_EMPTY_INT | CIX_FIFO_OFLOW_INT);
cix_mbox_write(priv, val, CIX_INT_ENABLE);
} else if (priv->dir == CIX_MBOX_RX) {
/* Disable fifo WM01/underflow interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
val &= ~(CIX_FIFO_UFLOW_INT | CIX_FIFO_WM01_INT);
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
}
break;
case CIX_MBOX_TYPE_FAST:
if (priv->dir == CIX_MBOX_RX) {
if (index < 0 || index > CIX_MBOX_FAST_IDX) {
dev_err(priv->dev, "Invalid index %d\n", index);
break;
}
/* Disable fast channel interrupt */
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
val &= ~CIX_FAST_CH_INT(index);
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
}
break;
default:
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
break;
}
free_irq(priv->irq, chan);
}
static const struct mbox_chan_ops cix_mbox_chan_ops = {
.send_data = cix_mbox_send_data,
.startup = cix_mbox_startup,
.shutdown = cix_mbox_shutdown,
};
static void cix_mbox_init(struct cix_mbox_priv *priv)
{
struct cix_mbox_con_priv *cp;
int i;
for (i = 0; i < CIX_MBOX_CHANS; i++) {
cp = &priv->con_priv[i];
cp->index = i;
cp->chan = &priv->mbox_chans[i];
priv->mbox_chans[i].con_priv = cp;
if (cp->index <= CIX_MBOX_FAST_IDX)
cp->type = CIX_MBOX_TYPE_FAST;
if (cp->index == CIX_MBOX_DB_IDX)
cp->type = CIX_MBOX_TYPE_DB;
if (cp->index == CIX_MBOX_FIFO_IDX)
cp->type = CIX_MBOX_TYPE_FIFO;
if (cp->index == CIX_MBOX_REG_IDX)
cp->type = CIX_MBOX_TYPE_REG;
}
}
static int cix_mbox_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cix_mbox_priv *priv;
struct resource *res;
const char *dir_str;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
/*
* The first 0x80 bytes of the register space of the cix mailbox controller
* can be used as shared memory for clients. When this shared memory is in
* use, the base address of the mailbox is offset by 0x80. Therefore, when
* performing subsequent read/write operations, it is necessary to subtract
* the offset CIX_SHMEM_OFFSET.
*
* When the base address of the mailbox is offset by 0x80, it indicates
* that shmem is in use.
*/
priv->use_shmem = !!(res->start & CIX_SHMEM_OFFSET);
priv->irq = platform_get_irq(pdev, 0);
if (priv->irq < 0)
return priv->irq;
if (device_property_read_string(dev, "cix,mbox-dir", &dir_str)) {
dev_err(priv->dev, "cix,mbox_dir property not found\n");
return -EINVAL;
}
if (!strcmp(dir_str, "tx"))
priv->dir = 0;
else if (!strcmp(dir_str, "rx"))
priv->dir = 1;
else {
dev_err(priv->dev, "cix,mbox_dir=%s is not expected\n", dir_str);
return -EINVAL;
}
cix_mbox_init(priv);
priv->mbox.dev = dev;
priv->mbox.ops = &cix_mbox_chan_ops;
priv->mbox.chans = priv->mbox_chans;
priv->mbox.txdone_irq = true;
priv->mbox.num_chans = CIX_MBOX_CHANS;
priv->mbox.of_xlate = NULL;
platform_set_drvdata(pdev, priv);
ret = devm_mbox_controller_register(dev, &priv->mbox);
if (ret)
dev_err(dev, "Failed to register mailbox %d\n", ret);
return ret;
}
static const struct of_device_id cix_mbox_dt_ids[] = {
{ .compatible = "cix,sky1-mbox" },
{ },
};
MODULE_DEVICE_TABLE(of, cix_mbox_dt_ids);
static struct platform_driver cix_mbox_driver = {
.probe = cix_mbox_probe,
.driver = {
.name = "cix_mbox",
.of_match_table = cix_mbox_dt_ids,
},
};
static int __init cix_mailbox_init(void)
{
return platform_driver_register(&cix_mbox_driver);
}
arch_initcall(cix_mailbox_init);
MODULE_AUTHOR("Cix Technology Group Co., Ltd.");
MODULE_DESCRIPTION("CIX mailbox driver");
MODULE_LICENSE("GPL");

279
include/dt-bindings/clock/cix,sky1.h Normal file
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@ -0,0 +1,279 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright 2024-2025 Cix Technology Group Co., Ltd.
*/
#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H
#define _DT_BINDINGS_CLK_CIX_SKY1_H
#define CLK_TREE_CPU_GICxCLK 0
#define CLK_TREE_CPU_PPUCLK 1
#define CLK_TREE_CPU_PERIPHCLK 2
#define CLK_TREE_DSU_CLK 3
#define CLK_TREE_DSU_PCLK 4
#define CLK_TREE_CPU_CLK_BC0 5
#define CLK_TREE_CPU_CLK_BC1 6
#define CLK_TREE_CPU_CLK_BC2 7
#define CLK_TREE_CPU_CLK_BC3 8
#define CLK_TREE_CPU_CLK_MC0 9
#define CLK_TREE_CPU_CLK_MC1 10
#define CLK_TREE_CPU_CLK_MC2 11
#define CLK_TREE_CPU_CLK_MC3 12
#define CLK_TREE_CPU_CLK_LC0 13
#define CLK_TREE_CPU_CLK_LC1 14
#define CLK_TREE_CPU_CLK_LC2 15
#define CLK_TREE_CPU_CLK_LC3 16
#define CLK_TREE_CSI_CTRL0_PCLK 17
#define CLK_TREE_CSI_CTRL1_PCLK 18
#define CLK_TREE_CSI_CTRL2_PCLK 19
#define CLK_TREE_CSI_CTRL3_PCLK 20
#define CLK_TREE_CSI_DMA0_PCLK 21
#define CLK_TREE_CSI_DMA1_PCLK 22
#define CLK_TREE_CSI_DMA2_PCLK 23
#define CLK_TREE_CSI_DMA3_PCLK 24
#define CLK_TREE_CSI_PHY0_PSM 25
#define CLK_TREE_CSI_PHY1_PSM 26
#define CLK_TREE_CSI_PHY0_APBCLK 27
#define CLK_TREE_CSI_PHY1_APBCLK 28
#define CLK_TREE_FCH_APB_CLK 29
#define CLK_TREE_GPU_CLK_400M 30
#define CLK_TREE_GPU_CLK_CORE 31
#define CLK_TREE_GPU_CLK_STACKS 32
#define CLK_TREE_DP0_PIXEL0 33
#define CLK_TREE_DP0_PIXEL1 34
#define CLK_TREE_DP1_PIXEL0 35
#define CLK_TREE_DP1_PIXEL1 36
#define CLK_TREE_DP2_PIXEL0 37
#define CLK_TREE_DP2_PIXEL1 38
#define CLK_TREE_DP3_PIXEL0 39
#define CLK_TREE_DP3_PIXEL1 40
#define CLK_TREE_DP4_PIXEL0 41
#define CLK_TREE_DP4_PIXEL1 42
#define CLK_TREE_DPU_CLK 43
#define CLK_TREE_DPU0_ACLK 44
#define CLK_TREE_DPU1_ACLK 45
#define CLK_TREE_DPU2_ACLK 46
#define CLK_TREE_DPU3_ACLK 47
#define CLK_TREE_DPU4_ACLK 48
#define CLK_TREE_DPC0_VIDCLK0 49
#define CLK_TREE_DPC0_VIDCLK1 50
#define CLK_TREE_DPC1_VIDCLK0 51
#define CLK_TREE_DPC1_VIDCLK1 52
#define CLK_TREE_DPC2_VIDCLK0 53
#define CLK_TREE_DPC2_VIDCLK1 54
#define CLK_TREE_DPC3_VIDCLK0 55
#define CLK_TREE_DPC3_VIDCLK1 56
#define CLK_TREE_DPC4_VIDCLK0 57
#define CLK_TREE_DPC4_VIDCLK1 58
#define CLK_TREE_DPC0_APBCLK 59
#define CLK_TREE_DPC1_APBCLK 60
#define CLK_TREE_DPC2_APBCLK 61
#define CLK_TREE_DPC3_APBCLK 62
#define CLK_TREE_DPC4_APBCLK 63
#define CLK_TREE_NPU_MEMCLK 64
#define CLK_TREE_NPU_SYSCLK 65
#define CLK_TREE_NPU_DBGCLK 66
#define CLK_TREE_VPU_APBCLK 67
#define CLK_TREE_ISP_ACLK 68
#define CLK_TREE_ISP_SCLK 69
#define CLK_TREE_AUDIO_CLK4 70
#define CLK_TREE_AUDIO_CLK5 71
#define CLK_TREE_CAMERA_MCLK0 72
#define CLK_TREE_CAMERA_MCLK1 73
#define CLK_TREE_CAMERA_MCLK2 74
#define CLK_TREE_CAMERA_MCLK3 75
#define CLK_TREE_AUDIO_CLK0 76
#define CLK_TREE_AUDIO_CLK1 77
#define CLK_TREE_AUDIO_CLK2 78
#define CLK_TREE_AUDIO_CLK3 79
#define CLK_TREE_MM_NI700_CLK 80
#define CLK_TREE_SYS_NI700_CLK 81
#define CLK_TREE_GMAC0_ACLK 82
#define CLK_TREE_GMAC1_ACLK 83
#define CLK_TREE_GMAC0_DIV_ACLK 84
#define CLK_TREE_GMAC0_DIV_TXCLK 85
#define CLK_TREE_GMAC0_RGMII0_TXCLK 86
#define CLK_TREE_GMAC1_DIV_ACLK 87
#define CLK_TREE_GMAC1_DIV_TXCLK 88
#define CLK_TREE_GMAC1_RGMII0_TXCLK 89
#define CLK_TREE_GMAC0_PCLK 90
#define CLK_TREE_GMAC1_PCLK 91
#define CLK_TREE_USB2_0_AXI_GATE 92
#define CLK_TREE_USB2_0_APB_GATE 93
#define CLK_TREE_USB2_1_AXI_GATE 94
#define CLK_TREE_USB2_1_APB_GATE 95
#define CLK_TREE_USB2_2_AXI_GATE 96
#define CLK_TREE_USB2_2_APB_GATE 97
#define CLK_TREE_USB2_3_AXI_GATE 98
#define CLK_TREE_USB2_3_APB_GATE 99
#define CLK_TREE_USB2_0_PHY_GATE 100
#define CLK_TREE_USB2_1_PHY_GATE 101
#define CLK_TREE_USB2_2_PHY_GATE 102
#define CLK_TREE_USB2_3_PHY_GATE 103
#define CLK_TREE_USB3C_DRD_AXI_GATE 104
#define CLK_TREE_USB3C_DRD_APB_GATE 105
#define CLK_TREE_USB3C_DRD_PHY2_GATE 106
#define CLK_TREE_USB3C_DRD_PHY3_GATE 107
#define CLK_TREE_USB3C_0_AXI_GATE 108
#define CLK_TREE_USB3C_0_APB_GATE 109
#define CLK_TREE_USB3C_0_PHY2_GATE 110
#define CLK_TREE_USB3C_0_PHY3_GATE 111
#define CLK_TREE_USB3C_1_AXI_GATE 112
#define CLK_TREE_USB3C_1_APB_GATE 113
#define CLK_TREE_USB3C_1_PHY2_GATE 114
#define CLK_TREE_USB3C_1_PHY3_GATE 115
#define CLK_TREE_USB3C_2_AXI_GATE 116
#define CLK_TREE_USB3C_2_APB_GATE 117
#define CLK_TREE_USB3C_2_PHY2_GATE 118
#define CLK_TREE_USB3C_2_PHY3_GATE 119
#define CLK_TREE_USB3A_0_AXI_GATE 120
#define CLK_TREE_USB3A_0_APB_GATE 121
#define CLK_TREE_USB3A_0_PHY2_GATE 122
#define CLK_TREE_USB3A_1_AXI_GATE 123
#define CLK_TREE_USB3A_1_APB_GATE 124
#define CLK_TREE_USB3A_1_PHY2_GATE 125
#define CLK_TREE_USB3A_PHY3_GATE 126
#define CLK_TREE_USB2_0_CLK_SOF 127
#define CLK_TREE_USB2_1_CLK_SOF 128
#define CLK_TREE_USB2_2_CLK_SOF 129
#define CLK_TREE_USB2_3_CLK_SOF 130
#define CLK_TREE_USB3C_DRD_CLK_SOF 131
#define CLK_TREE_USB3C_H0_CLK_SOF 132
#define CLK_TREE_USB3C_H1_CLK_SOF 133
#define CLK_TREE_USB3C_H2_CLK_SOF 134
#define CLK_TREE_USB3A_H0_CLK_SOF 135
#define CLK_TREE_USB3A_H1_CLK_SOF 136
#define CLK_TREE_USB2_0_CLK_LPM 137
#define CLK_TREE_USB2_1_CLK_LPM 138
#define CLK_TREE_USB2_2_CLK_LPM 139
#define CLK_TREE_USB2_3_CLK_LPM 140
#define CLK_TREE_USB3C_DRD_CLK_LPM 141
#define CLK_TREE_USB3C_H0_CLK_LPM 142
#define CLK_TREE_USB3C_H1_CLK_LPM 143
#define CLK_TREE_USB3C_H2_CLK_LPM 144
#define CLK_TREE_USB3A_H0_CLK_LPM 145
#define CLK_TREE_USB3A_H1_CLK_LPM 146
#define CLK_TREE_USB2_0_PHY_REF 147
#define CLK_TREE_USB2_1_PHY_REF 148
#define CLK_TREE_USB2_2_PHY_REF 149
#define CLK_TREE_USB2_3_PHY_REF 150
#define CLK_TREE_USB3C_DRD_PHY_REF 151
#define CLK_TREE_USB3C_H0_PHY_REF 152
#define CLK_TREE_USB3C_H1_PHY_REF 153
#define CLK_TREE_USB3C_H2_PHY_REF 154
#define CLK_TREE_USB3A_H0_PHY_REF 155
#define CLK_TREE_USB3A_H1_PHY_REF 156
#define CLK_TREE_USB3C_DRD_PHY_x4_REF 157
#define CLK_TREE_USB3C_H0_PHY_x4_REF 158
#define CLK_TREE_USB3C_H1_PHY_x4_REF 159
#define CLK_TREE_USB3C_H2_PHY_x4_REF 160
#define CLK_TREE_USB3A_PHY_x2_REF 161
#define CLK_TREE_PCIE_X8CTRL_APB 162
#define CLK_TREE_PCIE_X4CTRL_APB 163
#define CLK_TREE_PCIE_X2CTRL_APB 164
#define CLK_TREE_PCIE_X1_0CTRL_APB 165
#define CLK_TREE_PCIE_X1_1CTRL_APB 166
#define CLK_TREE_PCIE_X8_PHY_APB 167
#define CLK_TREE_PCIE_X4_PHY_APB 168
#define CLK_TREE_PCIE_X211_PHY_APB 169
#define CLK_TREE_PCIE_NI700_CLK 170
#define CLK_TREE_PCIE_CTRL0_CLK 171
#define CLK_TREE_PCIE_CTRL1_CLK 172
#define CLK_TREE_PCIE_CTRL2_CLK 173
#define CLK_TREE_PCIE_CTRL3_CLK 174
#define CLK_TREE_PCIE_CTRL4_CLK 175
#define CLK_TREE_CSI_CTRL0_SYSCLK 176
#define CLK_TREE_CSI_CTRL1_SYSCLK 177
#define CLK_TREE_CSI_CTRL2_SYSCLK 178
#define CLK_TREE_CSI_CTRL3_SYSCLK 179
#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK 180
#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK 181
#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK 182
#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK 183
#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK 184
#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK 185
#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK 186
#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK 187
#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK 188
#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK 189
#define CLK_TREE_CI700_GCLK0 190
#define CLK_TREE_DDRC0_ACLK_CLK 191
#define CLK_TREE_DDRC1_ACLK_CLK 192
#define CLK_TREE_DDRC2_ACLK_CLK 193
#define CLK_TREE_DDRC3_ACLK_CLK 194
#define CLK_TREE_DDRC0_DFICLK_CLK 195
#define CLK_TREE_DDRC1_DFICLK_CLK 196
#define CLK_TREE_DDRC2_DFICLK_CLK 197
#define CLK_TREE_DDRC3_DFICLK_CLK 198
#define CLK_TREE_PHY0_SYNC_CLK 199
#define CLK_TREE_PHY1_SYNC_CLK 200
#define CLK_TREE_PHY2_SYNC_CLK 201
#define CLK_TREE_PHY3_SYNC_CLK 202
#define CLK_TREE_PHY0_BYPASS_CLK 203
#define CLK_TREE_PHY1_BYPASS_CLK 204
#define CLK_TREE_PHY2_BYPASS_CLK 205
#define CLK_TREE_PHY3_BYPASS_CLK 206
#define CLK_TREE_DDRC_0_APB 207
#define CLK_TREE_DDRC_1_APB 208
#define CLK_TREE_DDRC_2_APB 209
#define CLK_TREE_DDRC_3_APB 210
#define CLK_TREE_TZC400_0_APB 211
#define CLK_TREE_TZC400_1_APB 212
#define CLK_TREE_TZC400_2_APB 213
#define CLK_TREE_TZC400_3_APB 214
#define CLK_TREE_S5_SENSOR_HUB_25M 215
#define CLK_TREE_S5_SENSOR_HUB_400M 216
#define CLK_TREE_S5_CSS600_100M 217
#define CLK_TREE_S5_DFD_800M 218
#define CLK_TREE_S5_CSU_SE_800M 219
#define CLK_TREE_S5_CSU_PM_800M 220
#define CLK_TREE_PCIE_REF_B0 221
#define CLK_TREE_PCIE_REF_B1 222
#define CLK_TREE_PCIE_REF_B2 223
#define CLK_TREE_PCIE_REF_B3 224
#define CLK_TREE_PCIE_REF_B4 225
#define CLK_TREE_PCIE_REF_PHY_X8 226
#define CLK_TREE_PCIE_REF_PHY_X4 227
#define CLK_TREE_PCIE_REF_PHY_X211 228
#define CLK_TREE_GMAC_REC_CLK 229
#define CLK_TREE_GPUTOP_PLL 230
#define CLK_TREE_GPUCORE_PLL 231
#define CLK_TREE_CPU_PLL_LIT 232
#define CLK_TREE_CPU_PLL0 233
#define CLK_TREE_CPU_PLL1 234
#define CLK_TREE_CPU_PLL2 235
#define CLK_TREE_CPU_PLL3 236
#define CLK_TREE_FCH_I3C0_FUNC 237
#define CLK_TREE_FCH_I3C1_FUNC 238
#define CLK_TREE_FCH_DMA_ACLK 239
#define CLK_TREE_FCH_XSPI_FUNC 240
#define CLK_TREE_FCH_XSPI_MACLK 241
#define CLK_TREE_FCH_TIMER_FUN 242
#define CLK_TREE_FCH_APB_IO_S0 243
#define CLK_TREE_FCH_I3C0_APB 244
#define CLK_TREE_FCH_I3C1_APB 245
#define CLK_TREE_FCH_UART0_APB 246
#define CLK_TREE_FCH_UART1_APB 247
#define CLK_TREE_FCH_UART2_APB 248
#define CLK_TREE_FCH_UART3_APB 249
#define CLK_TREE_FCH_SPI0_APB 250
#define CLK_TREE_FCH_SPI1_APB 251
#define CLK_TREE_FCH_XSPI_APB 252
#define CLK_TREE_FCH_I2C0_APB 253
#define CLK_TREE_FCH_I2C1_APB 254
#define CLK_TREE_FCH_I2C2_APB 255
#define CLK_TREE_FCH_I2C3_APB 256
#define CLK_TREE_FCH_I2C4_APB 257
#define CLK_TREE_FCH_I2C5_APB 258
#define CLK_TREE_FCH_I2C6_APB 259
#define CLK_TREE_FCH_I2C7_APB 260
#define CLK_TREE_FCH_TIMER_APB 261
#define CLK_TREE_FCH_GPIO_APB 262
#define CLK_TREE_FCH_UART0_FUNC 263
#define CLK_TREE_FCH_UART1_FUNC 264
#define CLK_TREE_FCH_UART2_FUNC 265
#define CLK_TREE_FCH_UART3_FUNC 266
/* 267~271 not used by AP, skip */
#define CLK_TREE_GPU_CLK_200M 272
#endif