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drm/i915: Test partial mappings
Create partial mappings to cover a large object, investigating tiling (fenced regions) and VMA reuse. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-19-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
12d30d8793
commit
48d8981720
1 changed files with 293 additions and 0 deletions
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@ -140,6 +140,298 @@ out:
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return err;
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}
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struct tile {
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unsigned int width;
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unsigned int height;
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unsigned int stride;
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unsigned int size;
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unsigned int tiling;
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unsigned int swizzle;
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};
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static u64 swizzle_bit(unsigned int bit, u64 offset)
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{
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return (offset & BIT_ULL(bit)) >> (bit - 6);
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}
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static u64 tiled_offset(const struct tile *tile, u64 v)
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{
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u64 x, y;
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if (tile->tiling == I915_TILING_NONE)
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return v;
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y = div64_u64_rem(v, tile->stride, &x);
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v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
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if (tile->tiling == I915_TILING_X) {
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v += y * tile->width;
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v += div64_u64_rem(x, tile->width, &x) << tile->size;
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v += x;
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} else {
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const unsigned int ytile_span = 16;
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const unsigned int ytile_height = 32 * ytile_span;
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v += y * ytile_span;
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v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
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v += x;
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}
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switch (tile->swizzle) {
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case I915_BIT_6_SWIZZLE_9:
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v ^= swizzle_bit(9, v);
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break;
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case I915_BIT_6_SWIZZLE_9_10:
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v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
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break;
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case I915_BIT_6_SWIZZLE_9_11:
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v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
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break;
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case I915_BIT_6_SWIZZLE_9_10_11:
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v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11, v);
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break;
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}
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return v;
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}
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static int check_partial_mapping(struct drm_i915_gem_object *obj,
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const struct tile *tile,
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unsigned long end_time)
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{
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const unsigned int nreal = obj->scratch / PAGE_SIZE;
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const unsigned long npages = obj->base.size / PAGE_SIZE;
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struct i915_vma *vma;
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unsigned long page;
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int err;
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if (igt_timeout(end_time,
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"%s: timed out before tiling=%d stride=%d\n",
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__func__, tile->tiling, tile->stride))
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return -EINTR;
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err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
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if (err)
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return err;
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GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
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GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
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for_each_prime_number_from(page, 1, npages) {
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struct i915_ggtt_view view =
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compute_partial_view(obj, page, MIN_CHUNK_PAGES);
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u32 __iomem *io;
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struct page *p;
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unsigned int n;
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u64 offset;
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u32 *cpu;
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GEM_BUG_ON(view.partial.size > nreal);
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err = i915_gem_object_set_to_gtt_domain(obj, true);
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if (err)
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return err;
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vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
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if (IS_ERR(vma)) {
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pr_err("Failed to pin partial view: offset=%lu\n",
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page);
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return PTR_ERR(vma);
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}
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n = page - view.partial.offset;
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GEM_BUG_ON(n >= view.partial.size);
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io = i915_vma_pin_iomap(vma);
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i915_vma_unpin(vma);
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if (IS_ERR(io)) {
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pr_err("Failed to iomap partial view: offset=%lu\n",
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page);
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return PTR_ERR(io);
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}
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err = i915_vma_get_fence(vma);
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if (err) {
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pr_err("Failed to get fence for partial view: offset=%lu\n",
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page);
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i915_vma_unpin_iomap(vma);
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return err;
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}
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iowrite32(page, io + n * PAGE_SIZE/sizeof(*io));
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i915_vma_unpin_iomap(vma);
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offset = tiled_offset(tile, page << PAGE_SHIFT);
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if (offset >= obj->base.size)
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continue;
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i915_gem_object_flush_gtt_write_domain(obj);
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p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
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cpu = kmap(p) + offset_in_page(offset);
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drm_clflush_virt_range(cpu, sizeof(*cpu));
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if (*cpu != (u32)page) {
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pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n",
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page, n,
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view.partial.offset,
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view.partial.size,
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vma->size >> PAGE_SHIFT,
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tile_row_pages(obj),
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vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
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offset >> PAGE_SHIFT,
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(unsigned int)offset_in_page(offset),
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offset,
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(u32)page, *cpu);
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err = -EINVAL;
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}
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*cpu = 0;
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drm_clflush_virt_range(cpu, sizeof(*cpu));
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kunmap(p);
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if (err)
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return err;
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}
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return 0;
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}
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static int igt_partial_tiling(void *arg)
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{
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const unsigned int nreal = 1 << 12; /* largest tile row x2 */
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_object *obj;
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int tiling;
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int err;
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/* We want to check the page mapping and fencing of a large object
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* mmapped through the GTT. The object we create is larger than can
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* possibly be mmaped as a whole, and so we must use partial GGTT vma.
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* We then check that a write through each partial GGTT vma ends up
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* in the right set of pages within the object, and with the expected
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* tiling, which we verify by manual swizzling.
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*/
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obj = huge_gem_object(i915,
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nreal << PAGE_SHIFT,
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(1 + next_prime_number(i915->ggtt.base.total >> PAGE_SHIFT)) << PAGE_SHIFT);
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if (IS_ERR(obj))
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return PTR_ERR(obj);
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err = i915_gem_object_pin_pages(obj);
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if (err) {
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pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
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nreal, obj->base.size / PAGE_SIZE, err);
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goto out;
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}
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mutex_lock(&i915->drm.struct_mutex);
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if (1) {
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IGT_TIMEOUT(end);
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struct tile tile;
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tile.height = 1;
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tile.width = 1;
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tile.size = 0;
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tile.stride = 0;
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tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
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tile.tiling = I915_TILING_NONE;
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err = check_partial_mapping(obj, &tile, end);
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if (err && err != -EINTR)
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goto out_unlock;
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}
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for (tiling = I915_TILING_X; tiling <= I915_TILING_Y; tiling++) {
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IGT_TIMEOUT(end);
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unsigned int max_pitch;
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unsigned int pitch;
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struct tile tile;
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tile.tiling = tiling;
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switch (tiling) {
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case I915_TILING_X:
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tile.swizzle = i915->mm.bit_6_swizzle_x;
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break;
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case I915_TILING_Y:
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tile.swizzle = i915->mm.bit_6_swizzle_y;
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break;
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}
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if (tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN ||
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tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
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continue;
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if (INTEL_GEN(i915) <= 2) {
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tile.height = 16;
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tile.width = 128;
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tile.size = 11;
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} else if (tile.tiling == I915_TILING_Y &&
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HAS_128_BYTE_Y_TILING(i915)) {
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tile.height = 32;
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tile.width = 128;
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tile.size = 12;
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} else {
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tile.height = 8;
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tile.width = 512;
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tile.size = 12;
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}
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if (INTEL_GEN(i915) < 4)
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max_pitch = 8192 / tile.width;
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else if (INTEL_GEN(i915) < 7)
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max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width;
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else
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max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width;
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for (pitch = max_pitch; pitch; pitch >>= 1) {
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tile.stride = tile.width * pitch;
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err = check_partial_mapping(obj, &tile, end);
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if (err == -EINTR)
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goto next_tiling;
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if (err)
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goto out_unlock;
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if (pitch > 2 && INTEL_GEN(i915) >= 4) {
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tile.stride = tile.width * (pitch - 1);
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err = check_partial_mapping(obj, &tile, end);
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if (err == -EINTR)
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goto next_tiling;
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if (err)
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goto out_unlock;
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}
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if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
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tile.stride = tile.width * (pitch + 1);
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err = check_partial_mapping(obj, &tile, end);
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if (err == -EINTR)
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goto next_tiling;
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if (err)
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goto out_unlock;
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}
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}
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if (INTEL_GEN(i915) >= 4) {
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for_each_prime_number(pitch, max_pitch) {
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tile.stride = tile.width * pitch;
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err = check_partial_mapping(obj, &tile, end);
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if (err == -EINTR)
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goto next_tiling;
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if (err)
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goto out_unlock;
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}
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}
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next_tiling: ;
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}
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out_unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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i915_gem_object_unpin_pages(obj);
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out:
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i915_gem_object_put(obj);
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return err;
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}
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int i915_gem_object_mock_selftests(void)
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{
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static const struct i915_subtest tests[] = {
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@ -163,6 +455,7 @@ int i915_gem_object_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_gem_huge),
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SUBTEST(igt_partial_tiling),
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};
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return i915_subtests(tests, i915);
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