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dt-bindings: pinctrl: Convert i.MX7D to json-schema
Convert the i.MX7D pinctrl binding to DT schema format using json-schema Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220303150653.1903910-1-alexander.stein@ew.tq-group.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Alexander Stein
Linus Walleij
parent
94d93c9b74
commit
4764f39e36
2 changed files with 113 additions and 87 deletions
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* Freescale i.MX7 Dual IOMUX Controller
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iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
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as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
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power state retention capabilities on gpios that are part of iomuxc-lpsr
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(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
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mux and pad control settings, it shares the input select register from main
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iomuxc controller for daisy chain settings, the fsl,input-sel property extends
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fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
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iomuxc_lpsr: iomuxc-lpsr@302c0000 {
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compatible = "fsl,imx7d-iomuxc-lpsr";
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reg = <0x302c0000 0x10000>;
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fsl,input-sel = <&iomuxc>;
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};
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iomuxc: iomuxc@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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};
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Peripherals using pads from iomuxc-lpsr support low state retention power
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state, under LPSR mode GPIO's state of pads are retain.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
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and usage.
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Required properties:
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- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
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"fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
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- fsl,pins: each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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input_val> are specified using a PIN_FUNC_ID macro, which can be found in
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imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
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the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
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Reference Manual for detailed CONFIG settings.
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- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
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a phandle for main iomuxc controller which shares the input select register for
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daisy chain settings.
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CONFIG bits definition:
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PAD_CTL_PUS_100K_DOWN (0 << 5)
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PAD_CTL_PUS_5K_UP (1 << 5)
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PAD_CTL_PUS_47K_UP (2 << 5)
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PAD_CTL_PUS_100K_UP (3 << 5)
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PAD_CTL_PUE (1 << 4)
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PAD_CTL_HYS (1 << 3)
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PAD_CTL_SRE_SLOW (1 << 2)
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PAD_CTL_SRE_FAST (0 << 2)
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PAD_CTL_DSE_X1 (0 << 0)
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PAD_CTL_DSE_X4 (1 << 0)
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PAD_CTL_DSE_X2 (2 << 0)
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PAD_CTL_DSE_X6 (3 << 0)
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Examples:
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While iomuxc-lpsr is intended to be used by dedicated peripherals to take
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advantages of LPSR power mode, is also possible that an IP to use pads from
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any of the iomux controllers. For example the I2C1 IP can use SCL pad from
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iomuxc-lpsr controller and SDA pad from iomuxc controller as:
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i2c1: i2c@30a20000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>;
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};
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iomuxc-lpsr@302c0000 {
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compatible = "fsl,imx7d-iomuxc-lpsr";
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reg = <0x302c0000 0x10000>;
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fsl,input-sel = <&iomuxc>;
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pinctrl_i2c1_1: i2c1grp-1 {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
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>;
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};
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};
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iomuxc@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_i2c1_2: i2c1grp-2 {
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fsl,pins = <
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
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>;
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};
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};
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113
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
Normal file
113
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
Normal file
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@ -0,0 +1,113 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX7D IOMUX Controller
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maintainers:
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- Dong Aisheng <aisheng.dong@nxp.com>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx7d-iomuxc
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- fsl,imx7d-iomuxc-lpsr
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reg:
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maxItems: 1
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fsl,input-sel:
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description:
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phandle for main iomuxc controller which shares the input select
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register for daisy chain settings.
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$ref: /schemas/types.yaml#/definitions/phandle
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer
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CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX7D Reference Manual for detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_val" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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required:
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- fsl,pins
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additionalProperties: false
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx7d-iomuxc-lpsr
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then:
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required:
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- fsl,input-sel
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additionalProperties: false
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examples:
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_uart5: uart5grp {
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fsl,pins =
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<0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
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<0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
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};
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};
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- |
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iomuxc_lpsr: pinctrl@302c0000 {
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compatible = "fsl,imx7d-iomuxc-lpsr";
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reg = <0x302c0000 0x10000>;
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fsl,input-sel = <&iomuxc>;
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pinctrl_gpio_lpsr: gpio1-grp {
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fsl,pins =
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<0x0008 0x0038 0x0000 0x0 0x0 0x59>,
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<0x000C 0x003C 0x0000 0x0 0x0 0x59>;
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};
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};
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