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arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id

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Add gpio0 controller node and correct DMA handshake ID for SPI
tx and rx channels.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Niravkumar L Rabara 2024-12-04 14:32:54 +08:00 • committed by Dinh Nguyen
parent 8b87f3e333
commit 3f7c869e14
1 changed files with 23 additions and 1 deletions
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24
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
View file

@ -222,6 +222,26 @@
status = "disabled"; status = "disabled";
}; };
gpio0: gpio@ffc03200 {
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@10c03300 { gpio1: gpio@10c03300 {
compatible = "snps,dw-apb-gpio"; compatible = "snps,dw-apb-gpio";
reg = <0x10c03300 0x100>; reg = <0x10c03300 0x100>;
@ -314,7 +334,7 @@
reg-io-width = <4>; reg-io-width = <4>;
num-cs = <4>; num-cs = <4>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
dmas = <&dmac0 2>, <&dmac0 3>; dmas = <&dmac0 16>, <&dmac0 17>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
@ -331,6 +351,8 @@
reg-io-width = <4>; reg-io-width = <4>;
num-cs = <4>; num-cs = <4>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
dmas = <&dmac0 20>, <&dmac0 21>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };