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ARM: dts: ixp4xx: Group PCI interrupt properties together

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Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties
alongside the 'interrupt-map' property in each board dts. This avoids
having incomplete set of interrupt properties which may fail validation.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring 2021-09-28 14:21:22 -05:00 • committed by Linus Walleij
parent 7a4d10a17c
commit 3e70cee46c
13 changed files with 24 additions and 2 deletions
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2
arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
View file

@ -63,6 +63,8 @@
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */

2
arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
View file

@ -120,6 +120,8 @@
* We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
* per slot. This interrupt is shared (OR:ed) by all four pins.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */

2
arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
View file

@ -129,6 +129,8 @@
* We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
* Only slot 3 have three IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */

2
arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
View file

@ -106,6 +106,8 @@
* Written based on the FSG-3 PCI boardfile.
* We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */

2
arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
View file

@ -115,6 +115,8 @@
*
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

2
arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
View file

@ -115,6 +115,8 @@
* Taken from NAS 100D PCI boardfile (nas100d-pci.c)
* We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

2
arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
View file

@ -68,6 +68,8 @@
* We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
* for 12 & 13 and one for 14.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */

2
arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
View file

@ -122,6 +122,8 @@
* Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
* We have slots (IDSEL) 1, 2 and 3.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

2
arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
View file

@ -123,6 +123,8 @@
* We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
* Derived from the GTWX5715 PCI boardfile.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 0 */
<0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */

2
arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
View file

@ -62,6 +62,8 @@
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */

2
arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
View file

@ -131,6 +131,8 @@
* have instead assumed that they are rotated (swizzled) like
* this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

2
arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
View file

@ -106,6 +106,8 @@
* PCI slots on the BIXMB425BD base card.
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

2
arch/arm/boot/dts/intel-ixp4xx.dtsi
View file

@ -78,8 +78,6 @@
dma-ranges =
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
/* Each unique DTS using PCI must specify the swizzling */
};