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drm/i915: MCH_SSKPD is a 64 bit register on Haswell

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And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2013-05-03 17:23:44 -03:00 • committed by Daniel Vetter
parent 85a02deb4c
commit 3e1f72664e
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -4633,7 +4633,7 @@ void intel_init_pm(struct drm_device *dev)
} }
dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
} else if (IS_HASWELL(dev)) { } else if (IS_HASWELL(dev)) {
if (SNB_READ_WM0_LATENCY()) { if (I915_READ64(MCH_SSKPD)) {
dev_priv->display.update_wm = haswell_update_wm; dev_priv->display.update_wm = haswell_update_wm;
dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
} else { } else {