public-mirrors/linux
1
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-08-05 16:54:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

drm/i915: Always use INTEL_INFO() to access the device_info structure

Browse source 
If we make sure that all the dev_priv->info usages are wrapped by
INTEL_INFO(), we can easily modify the ->info field to be structure and
not a pointer while keeping the const protection in the INTEL_INFO()
macro.

v2: Rebased onto latest drm-nightly

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2014-02-07 19:12:47 +00:00 • committed by Daniel Vetter
parent e927ecde59
commit 3d13ef2e2d
4 changed files with 29 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/gpu/drm/i915/i915_gem.c
View file

@ -1014,7 +1014,8 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
struct timespec *timeout, struct timespec *timeout,
struct drm_i915_file_private *file_priv) struct drm_i915_file_private *file_priv)
{ {
drm_i915_private_t *dev_priv = ring->dev->dev_private; struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
const bool irq_test_in_progress = const bool irq_test_in_progress =
ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
struct timespec before, now; struct timespec before, now;
@ -1029,7 +1030,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) { if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
gen6_rps_boost(dev_priv); gen6_rps_boost(dev_priv);
if (file_priv) if (file_priv)
mod_delayed_work(dev_priv->wq, mod_delayed_work(dev_priv->wq,

4
drivers/gpu/drm/i915/i915_irq.c
View file

@ -2276,7 +2276,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
PIPE_VBLANK_INTERRUPT_ENABLE); PIPE_VBLANK_INTERRUPT_ENABLE);
/* maintain vblank delivery even in deep C-states */ /* maintain vblank delivery even in deep C-states */
if (dev_priv->info->gen == 3) if (INTEL_INFO(dev)->gen == 3)
I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@ -2341,7 +2341,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
unsigned long irqflags; unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags); spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
if (dev_priv->info->gen == 3) if (INTEL_INFO(dev)->gen == 3)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
i915_disable_pipestat(dev_priv, pipe, i915_disable_pipestat(dev_priv, pipe,

27
drivers/gpu/drm/i915/intel_display.c
View file

@ -1030,7 +1030,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
u32 val; u32 val;
/* ILK FDI PLL is always enabled */ /* ILK FDI PLL is always enabled */
if (dev_priv->info->gen == 5) if (INTEL_INFO(dev_priv->dev)->gen == 5)
return; return;
/* On Haswell, DDI ports are responsible for the FDI PLL setup */ /* On Haswell, DDI ports are responsible for the FDI PLL setup */
@ -1443,7 +1443,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
assert_pipe_disabled(dev_priv, crtc->pipe); assert_pipe_disabled(dev_priv, crtc->pipe);
/* No really, not for ILK+ */ /* No really, not for ILK+ */
BUG_ON(dev_priv->info->gen >= 5); BUG_ON(INTEL_INFO(dev)->gen >= 5);
/* PLL is protected by panel, make sure we can write it */ /* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev) && !IS_I830(dev)) if (IS_MOBILE(dev) && !IS_I830(dev))
@ -1549,11 +1549,12 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
*/ */
static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
/* PCH PLLs only available on ILK, SNB and IVB */ /* PCH PLLs only available on ILK, SNB and IVB */
BUG_ON(dev_priv->info->gen < 5); BUG_ON(INTEL_INFO(dev)->gen < 5);
if (WARN_ON(pll == NULL)) if (WARN_ON(pll == NULL))
return; return;
@ -1578,11 +1579,12 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
static void intel_disable_shared_dpll(struct intel_crtc *crtc) static void intel_disable_shared_dpll(struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
/* PCH only available on ILK+ */ /* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5); BUG_ON(INTEL_INFO(dev)->gen < 5);
if (WARN_ON(pll == NULL)) if (WARN_ON(pll == NULL))
return; return;
@ -1617,7 +1619,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
uint32_t reg, val, pipeconf_val; uint32_t reg, val, pipeconf_val;
/* PCH only available on ILK+ */ /* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5); BUG_ON(INTEL_INFO(dev)->gen < 5);
/* Make sure PCH DPLL is enabled */ /* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv, assert_shared_dpll_enabled(dev_priv,
@ -1670,7 +1672,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
u32 val, pipeconf_val; u32 val, pipeconf_val;
/* PCH only available on ILK+ */ /* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5); BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
/* FDI must be feeding us bits for PCH ports */ /* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
@ -1851,7 +1853,8 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
void intel_flush_primary_plane(struct drm_i915_private *dev_priv, void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane) enum plane plane)
{ {
u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); struct drm_device *dev = dev_priv->dev;
u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
I915_WRITE(reg, I915_READ(reg)); I915_WRITE(reg, I915_READ(reg));
POSTING_READ(reg); POSTING_READ(reg);
@ -7577,7 +7580,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
/* we only need to pin inside GTT if cursor is non-phy */ /* we only need to pin inside GTT if cursor is non-phy */
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
if (!dev_priv->info->cursor_needs_physical) { if (!INTEL_INFO(dev)->cursor_needs_physical) {
unsigned alignment; unsigned alignment;
if (obj->tiling_mode) { if (obj->tiling_mode) {
@ -7625,7 +7628,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
finish: finish:
if (intel_crtc->cursor_bo) { if (intel_crtc->cursor_bo) {
if (dev_priv->info->cursor_needs_physical) { if (INTEL_INFO(dev)->cursor_needs_physical) {
if (intel_crtc->cursor_bo != obj) if (intel_crtc->cursor_bo != obj)
i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
} else } else
@ -8220,7 +8223,7 @@ void intel_mark_idle(struct drm_device *dev)
intel_decrease_pllclock(crtc); intel_decrease_pllclock(crtc);
} }
if (dev_priv->info->gen >= 6) if (INTEL_INFO(dev)->gen >= 6)
gen6_rps_idle(dev->dev_private); gen6_rps_idle(dev->dev_private);
} }

13
drivers/gpu/drm/i915/intel_pm.c
View file

@ -3903,9 +3903,10 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{ {
struct drm_device *dev = dev_priv->dev;
unsigned long val; unsigned long val;
if (dev_priv->info->gen != 5) if (INTEL_INFO(dev)->gen != 5)
return 0; return 0;
spin_lock_irq(&mchdev_lock); spin_lock_irq(&mchdev_lock);
@ -3934,6 +3935,7 @@ unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{ {
struct drm_device *dev = dev_priv->dev;
static const struct v_table { static const struct v_table {
u16 vd; /* in .1 mil */ u16 vd; /* in .1 mil */
u16 vm; /* in .1 mil */ u16 vm; /* in .1 mil */
@ -4067,7 +4069,7 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{ 16000, 14875, }, { 16000, 14875, },
{ 16125, 15000, }, { 16125, 15000, },
}; };
if (dev_priv->info->is_mobile) if (INTEL_INFO(dev)->is_mobile)
return v_table[pxvid].vm; return v_table[pxvid].vm;
else else
return v_table[pxvid].vd; return v_table[pxvid].vd;
@ -4110,7 +4112,9 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
void i915_update_gfx_val(struct drm_i915_private *dev_priv) void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{ {
if (dev_priv->info->gen != 5) struct drm_device *dev = dev_priv->dev;
if (INTEL_INFO(dev)->gen != 5)
return; return;
spin_lock_irq(&mchdev_lock); spin_lock_irq(&mchdev_lock);
@ -4159,9 +4163,10 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
{ {
struct drm_device *dev = dev_priv->dev;
unsigned long val; unsigned long val;
if (dev_priv->info->gen != 5) if (INTEL_INFO(dev)->gen != 5)
return 0; return 0;
spin_lock_irq(&mchdev_lock); spin_lock_irq(&mchdev_lock);