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tty: serial: fsl_lpuart: use port struct directly to simply code
Most lpuart functions have the parameter struct uart_port *port, but still use the &sport->port to get the uart_port instead of use it directly, let's simply the code logic, directly use this struct instead of covert it from struct sport. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Link: https://lore.kernel.org/r/20250312023904.1343351-3-sherry.sun@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sherry Sun
Greg Kroah-Hartman
parent
b6a8f6ab2c
commit
3cc16ae096
1 changed files with 102 additions and 108 deletions
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@ -581,7 +581,7 @@ static int lpuart_dma_tx_request(struct uart_port *port)
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ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
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if (ret) {
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dev_err(sport->port.dev,
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dev_err(port->dev,
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"DMA slave config failed, err = %d\n", ret);
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return ret;
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}
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@ -611,13 +611,13 @@ static void lpuart_flush_buffer(struct uart_port *port)
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}
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if (lpuart_is_32(sport)) {
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val = lpuart32_read(&sport->port, UARTFIFO);
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val = lpuart32_read(port, UARTFIFO);
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val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
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lpuart32_write(&sport->port, val, UARTFIFO);
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lpuart32_write(port, val, UARTFIFO);
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} else {
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val = readb(sport->port.membase + UARTCFIFO);
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val = readb(port->membase + UARTCFIFO);
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val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
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writeb(val, sport->port.membase + UARTCFIFO);
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writeb(val, port->membase + UARTCFIFO);
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}
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}
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@ -644,33 +644,33 @@ static int lpuart_poll_init(struct uart_port *port)
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unsigned long flags;
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u8 temp;
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sport->port.fifosize = 0;
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port->fifosize = 0;
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uart_port_lock_irqsave(&sport->port, &flags);
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uart_port_lock_irqsave(port, &flags);
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/* Disable Rx & Tx */
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writeb(0, sport->port.membase + UARTCR2);
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writeb(0, port->membase + UARTCR2);
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temp = readb(sport->port.membase + UARTPFIFO);
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temp = readb(port->membase + UARTPFIFO);
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/* Enable Rx and Tx FIFO */
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writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
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sport->port.membase + UARTPFIFO);
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port->membase + UARTPFIFO);
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/* flush Tx and Rx FIFO */
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writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
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sport->port.membase + UARTCFIFO);
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port->membase + UARTCFIFO);
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/* explicitly clear RDRF */
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if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
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readb(sport->port.membase + UARTDR);
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writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
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if (readb(port->membase + UARTSR1) & UARTSR1_RDRF) {
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readb(port->membase + UARTDR);
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writeb(UARTSFIFO_RXUF, port->membase + UARTSFIFO);
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}
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writeb(0, sport->port.membase + UARTTWFIFO);
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writeb(1, sport->port.membase + UARTRWFIFO);
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writeb(0, port->membase + UARTTWFIFO);
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writeb(1, port->membase + UARTRWFIFO);
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/* Enable Rx and Tx */
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writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
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uart_port_unlock_irqrestore(&sport->port, flags);
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writeb(UARTCR2_RE | UARTCR2_TE, port->membase + UARTCR2);
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uart_port_unlock_irqrestore(port, flags);
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return 0;
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}
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@ -696,30 +696,30 @@ static int lpuart32_poll_init(struct uart_port *port)
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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u32 temp;
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sport->port.fifosize = 0;
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port->fifosize = 0;
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uart_port_lock_irqsave(&sport->port, &flags);
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uart_port_lock_irqsave(port, &flags);
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/* Disable Rx & Tx */
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lpuart32_write(&sport->port, 0, UARTCTRL);
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lpuart32_write(port, 0, UARTCTRL);
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temp = lpuart32_read(&sport->port, UARTFIFO);
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temp = lpuart32_read(port, UARTFIFO);
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/* Enable Rx and Tx FIFO */
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lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
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lpuart32_write(port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
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/* flush Tx and Rx FIFO */
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lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
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lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
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/* explicitly clear RDRF */
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if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
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lpuart32_read(&sport->port, UARTDATA);
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lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
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if (lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF) {
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lpuart32_read(port, UARTDATA);
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lpuart32_write(port, UARTFIFO_RXUF, UARTFIFO);
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}
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/* Enable Rx and Tx */
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lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
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uart_port_unlock_irqrestore(&sport->port, flags);
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lpuart32_write(port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
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uart_port_unlock_irqrestore(port, flags);
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return 0;
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}
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@ -1449,12 +1449,9 @@ static void lpuart_dma_rx_free(struct uart_port *port)
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static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
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struct serial_rs485 *rs485)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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u8 modem = readb(sport->port.membase + UARTMODEM) &
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u8 modem = readb(port->membase + UARTMODEM) &
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~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
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writeb(modem, sport->port.membase + UARTMODEM);
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writeb(modem, port->membase + UARTMODEM);
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if (rs485->flags & SER_RS485_ENABLED) {
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/* Enable auto RS-485 RTS mode */
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@ -1472,32 +1469,29 @@ static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
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modem &= ~UARTMODEM_TXRTSPOL;
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}
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writeb(modem, sport->port.membase + UARTMODEM);
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writeb(modem, port->membase + UARTMODEM);
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return 0;
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}
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static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
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struct serial_rs485 *rs485)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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u32 modem = lpuart32_read(&sport->port, UARTMODIR)
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u32 modem = lpuart32_read(port, UARTMODIR)
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& ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
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u32 ctrl;
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/* TXRTSE and TXRTSPOL only can be changed when transmitter is disabled. */
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ctrl = lpuart32_read(&sport->port, UARTCTRL);
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ctrl = lpuart32_read(port, UARTCTRL);
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if (ctrl & UARTCTRL_TE) {
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/* wait for the transmit engine to complete */
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lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
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lpuart32_write(&sport->port, ctrl & ~UARTCTRL_TE, UARTCTRL);
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lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC);
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lpuart32_write(port, ctrl & ~UARTCTRL_TE, UARTCTRL);
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while (lpuart32_read(&sport->port, UARTCTRL) & UARTCTRL_TE)
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while (lpuart32_read(port, UARTCTRL) & UARTCTRL_TE)
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cpu_relax();
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}
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lpuart32_write(&sport->port, modem, UARTMODIR);
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lpuart32_write(port, modem, UARTMODIR);
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if (rs485->flags & SER_RS485_ENABLED) {
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/* Enable auto RS-485 RTS mode */
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@ -1515,10 +1509,10 @@ static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termio
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modem &= ~UARTMODIR_TXRTSPOL;
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}
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lpuart32_write(&sport->port, modem, UARTMODIR);
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lpuart32_write(port, modem, UARTMODIR);
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if (ctrl & UARTCTRL_TE)
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lpuart32_write(&sport->port, ctrl, UARTCTRL);
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lpuart32_write(port, ctrl, UARTCTRL);
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return 0;
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}
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@ -1829,11 +1823,11 @@ static int lpuart_startup(struct uart_port *port)
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u8 temp;
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/* determine FIFO size and enable FIFO mode */
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temp = readb(sport->port.membase + UARTPFIFO);
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temp = readb(port->membase + UARTPFIFO);
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sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
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UARTPFIFO_FIFOSIZE_MASK);
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sport->port.fifosize = sport->txfifo_size;
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port->fifosize = sport->txfifo_size;
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sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
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UARTPFIFO_FIFOSIZE_MASK);
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@ -1889,11 +1883,11 @@ static int lpuart32_startup(struct uart_port *port)
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u32 temp;
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/* determine FIFO size */
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temp = lpuart32_read(&sport->port, UARTFIFO);
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temp = lpuart32_read(port, UARTFIFO);
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sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
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UARTFIFO_FIFOSIZE_MASK);
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sport->port.fifosize = sport->txfifo_size;
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port->fifosize = sport->txfifo_size;
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sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
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UARTFIFO_FIFOSIZE_MASK);
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@ -1906,7 +1900,7 @@ static int lpuart32_startup(struct uart_port *port)
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if (is_layerscape_lpuart(sport)) {
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sport->rxfifo_size = 16;
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sport->txfifo_size = 16;
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sport->port.fifosize = sport->txfifo_size;
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port->fifosize = sport->txfifo_size;
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}
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lpuart_request_dma(sport);
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@ -1966,8 +1960,8 @@ static void lpuart32_shutdown(struct uart_port *port)
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uart_port_lock_irqsave(port, &flags);
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/* clear status */
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temp = lpuart32_read(&sport->port, UARTSTAT);
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lpuart32_write(&sport->port, temp, UARTSTAT);
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temp = lpuart32_read(port, UARTSTAT);
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lpuart32_write(port, temp, UARTSTAT);
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/* disable Rx/Tx DMA */
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temp = lpuart32_read(port, UARTBAUD);
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@ -2001,12 +1995,12 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
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unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
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unsigned int sbr, brfa;
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cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
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old_cr2 = readb(sport->port.membase + UARTCR2);
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cr3 = readb(sport->port.membase + UARTCR3);
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cr4 = readb(sport->port.membase + UARTCR4);
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bdh = readb(sport->port.membase + UARTBDH);
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modem = readb(sport->port.membase + UARTMODEM);
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cr1 = old_cr1 = readb(port->membase + UARTCR1);
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old_cr2 = readb(port->membase + UARTCR2);
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cr3 = readb(port->membase + UARTCR3);
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cr4 = readb(port->membase + UARTCR4);
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bdh = readb(port->membase + UARTBDH);
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modem = readb(port->membase + UARTMODEM);
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/*
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* only support CS8 and CS7, and for CS7 must enable PE.
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* supported mode:
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@ -2038,7 +2032,7 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
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* When auto RS-485 RTS mode is enabled,
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* hardware flow control need to be disabled.
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*/
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if (sport->port.rs485.flags & SER_RS485_ENABLED)
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if (port->rs485.flags & SER_RS485_ENABLED)
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termios->c_cflag &= ~CRTSCTS;
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if (termios->c_cflag & CRTSCTS)
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@ -2079,59 +2073,59 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
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* Need to update the Ring buffer length according to the selected
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* baud rate and restart Rx DMA path.
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*
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* Since timer function acqures sport->port.lock, need to stop before
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* Since timer function acqures port->lock, need to stop before
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* acquring same lock because otherwise del_timer_sync() can deadlock.
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*/
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if (old && sport->lpuart_dma_rx_use)
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lpuart_dma_rx_free(&sport->port);
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lpuart_dma_rx_free(port);
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uart_port_lock_irqsave(&sport->port, &flags);
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uart_port_lock_irqsave(port, &flags);
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sport->port.read_status_mask = 0;
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port->read_status_mask = 0;
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if (termios->c_iflag & INPCK)
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sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
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port->read_status_mask |= UARTSR1_FE | UARTSR1_PE;
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if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
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sport->port.read_status_mask |= UARTSR1_FE;
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port->read_status_mask |= UARTSR1_FE;
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/* characters to ignore */
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sport->port.ignore_status_mask = 0;
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port->ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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sport->port.ignore_status_mask |= UARTSR1_PE;
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port->ignore_status_mask |= UARTSR1_PE;
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if (termios->c_iflag & IGNBRK) {
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sport->port.ignore_status_mask |= UARTSR1_FE;
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port->ignore_status_mask |= UARTSR1_FE;
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/*
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* if we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (termios->c_iflag & IGNPAR)
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sport->port.ignore_status_mask |= UARTSR1_OR;
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port->ignore_status_mask |= UARTSR1_OR;
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}
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/* update the per-port timeout */
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uart_update_timeout(port, termios->c_cflag, baud);
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/* wait transmit engin complete */
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lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
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lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TC);
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/* disable transmit and receive */
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writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
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sport->port.membase + UARTCR2);
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port->membase + UARTCR2);
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sbr = sport->port.uartclk / (16 * baud);
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brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
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sbr = port->uartclk / (16 * baud);
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brfa = ((port->uartclk - (16 * sbr * baud)) * 2) / baud;
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bdh &= ~UARTBDH_SBR_MASK;
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bdh |= (sbr >> 8) & 0x1F;
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cr4 &= ~UARTCR4_BRFA_MASK;
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brfa &= UARTCR4_BRFA_MASK;
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writeb(cr4 | brfa, sport->port.membase + UARTCR4);
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writeb(bdh, sport->port.membase + UARTBDH);
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writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
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writeb(cr3, sport->port.membase + UARTCR3);
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writeb(cr1, sport->port.membase + UARTCR1);
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writeb(modem, sport->port.membase + UARTMODEM);
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writeb(cr4 | brfa, port->membase + UARTCR4);
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writeb(bdh, port->membase + UARTBDH);
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writeb(sbr & 0xFF, port->membase + UARTBDL);
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writeb(cr3, port->membase + UARTCR3);
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writeb(cr1, port->membase + UARTCR1);
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writeb(modem, port->membase + UARTMODEM);
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/* restore control register */
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writeb(old_cr2, sport->port.membase + UARTCR2);
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writeb(old_cr2, port->membase + UARTCR2);
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if (old && sport->lpuart_dma_rx_use) {
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if (!lpuart_start_rx_dma(sport))
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@ -2140,7 +2134,7 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
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sport->lpuart_dma_rx_use = false;
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}
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uart_port_unlock_irqrestore(&sport->port, flags);
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uart_port_unlock_irqrestore(port, flags);
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}
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static void __lpuart32_serial_setbrg(struct uart_port *port,
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@ -2238,9 +2232,9 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
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unsigned int baud;
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unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
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ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
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bd = lpuart32_read(&sport->port, UARTBAUD);
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modem = lpuart32_read(&sport->port, UARTMODIR);
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ctrl = old_ctrl = lpuart32_read(port, UARTCTRL);
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||||
bd = lpuart32_read(port, UARTBAUD);
|
||||
modem = lpuart32_read(port, UARTMODIR);
|
||||
sport->is_cs7 = false;
|
||||
/*
|
||||
* only support CS8 and CS7
|
||||
|
|
@ -2274,7 +2268,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
* When auto RS-485 RTS mode is enabled,
|
||||
* hardware flow control need to be disabled.
|
||||
*/
|
||||
if (sport->port.rs485.flags & SER_RS485_ENABLED)
|
||||
if (port->rs485.flags & SER_RS485_ENABLED)
|
||||
termios->c_cflag &= ~CRTSCTS;
|
||||
|
||||
if (termios->c_cflag & CRTSCTS)
|
||||
|
|
@ -2324,32 +2318,32 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
* Need to update the Ring buffer length according to the selected
|
||||
* baud rate and restart Rx DMA path.
|
||||
*
|
||||
* Since timer function acqures sport->port.lock, need to stop before
|
||||
* Since timer function acqures port->lock, need to stop before
|
||||
* acquring same lock because otherwise del_timer_sync() can deadlock.
|
||||
*/
|
||||
if (old && sport->lpuart_dma_rx_use)
|
||||
lpuart_dma_rx_free(&sport->port);
|
||||
lpuart_dma_rx_free(port);
|
||||
|
||||
uart_port_lock_irqsave(&sport->port, &flags);
|
||||
uart_port_lock_irqsave(port, &flags);
|
||||
|
||||
sport->port.read_status_mask = 0;
|
||||
port->read_status_mask = 0;
|
||||
if (termios->c_iflag & INPCK)
|
||||
sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
|
||||
port->read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
|
||||
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
|
||||
sport->port.read_status_mask |= UARTSTAT_FE;
|
||||
port->read_status_mask |= UARTSTAT_FE;
|
||||
|
||||
/* characters to ignore */
|
||||
sport->port.ignore_status_mask = 0;
|
||||
port->ignore_status_mask = 0;
|
||||
if (termios->c_iflag & IGNPAR)
|
||||
sport->port.ignore_status_mask |= UARTSTAT_PE;
|
||||
port->ignore_status_mask |= UARTSTAT_PE;
|
||||
if (termios->c_iflag & IGNBRK) {
|
||||
sport->port.ignore_status_mask |= UARTSTAT_FE;
|
||||
port->ignore_status_mask |= UARTSTAT_FE;
|
||||
/*
|
||||
* if we're ignoring parity and break indicators,
|
||||
* ignore overruns too (for real raw support).
|
||||
*/
|
||||
if (termios->c_iflag & IGNPAR)
|
||||
sport->port.ignore_status_mask |= UARTSTAT_OR;
|
||||
port->ignore_status_mask |= UARTSTAT_OR;
|
||||
}
|
||||
|
||||
/* update the per-port timeout */
|
||||
|
|
@ -2361,22 +2355,22 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
* asserted.
|
||||
*/
|
||||
if (!(old_ctrl & UARTCTRL_SBK)) {
|
||||
lpuart32_write(&sport->port, 0, UARTMODIR);
|
||||
lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
|
||||
lpuart32_write(port, 0, UARTMODIR);
|
||||
lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC);
|
||||
}
|
||||
|
||||
/* disable transmit and receive */
|
||||
lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
|
||||
lpuart32_write(port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
|
||||
UARTCTRL);
|
||||
|
||||
lpuart32_write(&sport->port, bd, UARTBAUD);
|
||||
lpuart32_write(port, bd, UARTBAUD);
|
||||
lpuart32_serial_setbrg(sport, baud);
|
||||
/* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */
|
||||
lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
|
||||
lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
|
||||
/* restore control register */
|
||||
lpuart32_write(&sport->port, ctrl, UARTCTRL);
|
||||
lpuart32_write(port, ctrl, UARTCTRL);
|
||||
/* re-enable the CTS if needed */
|
||||
lpuart32_write(&sport->port, modem, UARTMODIR);
|
||||
lpuart32_write(port, modem, UARTMODIR);
|
||||
|
||||
if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
|
||||
sport->is_cs7 = true;
|
||||
|
|
@ -2388,7 +2382,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
sport->lpuart_dma_rx_use = false;
|
||||
}
|
||||
|
||||
uart_port_unlock_irqrestore(&sport->port, flags);
|
||||
uart_port_unlock_irqrestore(port, flags);
|
||||
}
|
||||
|
||||
static const char *lpuart_type(struct uart_port *port)
|
||||
|
|
@ -2826,7 +2820,7 @@ static int lpuart_global_reset(struct lpuart_port *sport)
|
|||
|
||||
ret = clk_prepare_enable(sport->ipg_clk);
|
||||
if (ret) {
|
||||
dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
|
||||
dev_err(port->dev, "failed to enable uart ipg clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -2837,10 +2831,10 @@ static int lpuart_global_reset(struct lpuart_port *sport)
|
|||
*/
|
||||
ctrl = lpuart32_read(port, UARTCTRL);
|
||||
if (ctrl & UARTCTRL_TE) {
|
||||
bd = lpuart32_read(&sport->port, UARTBAUD);
|
||||
bd = lpuart32_read(port, UARTBAUD);
|
||||
if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
|
||||
port)) {
|
||||
dev_warn(sport->port.dev,
|
||||
dev_warn(port->dev,
|
||||
"timeout waiting for transmit engine to complete\n");
|
||||
clk_disable_unprepare(sport->ipg_clk);
|
||||
return 0;
|
||||
|
|
@ -3192,7 +3186,7 @@ static void lpuart_console_fixup(struct lpuart_port *sport)
|
|||
* in VLLS mode, or restore console setting here.
|
||||
*/
|
||||
if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
|
||||
console_suspend_enabled && uart_console(&sport->port)) {
|
||||
console_suspend_enabled && uart_console(uport)) {
|
||||
|
||||
mutex_lock(&port->mutex);
|
||||
memset(&termios, 0, sizeof(struct ktermios));
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue