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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
media: qcom: camss: Add support for VFE 780
Add support for VFE found on SM8550 (Titan 780). This implementation is based on the titan 480 implementation. It supports the normal and lite VFE. Co-developed-by: Yongsheng Li <quic_yon@quicinc.com> Signed-off-by: Yongsheng Li <quic_yon@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Depeng Shao
Hans Verkuil
parent
d96fe1808d
commit
39e3f5bc0a
5 changed files with 284 additions and 0 deletions
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@ -17,6 +17,7 @@ qcom-camss-objs += \
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camss-vfe-4-8.o \
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camss-vfe-17x.o \
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camss-vfe-480.o \
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camss-vfe-780.o \
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camss-vfe-gen1.o \
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camss-vfe.o \
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camss-video.o \
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159
drivers/media/platform/qcom/camss/camss-vfe-780.c
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159
drivers/media/platform/qcom/camss/camss-vfe-780.c
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@ -0,0 +1,159 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550)
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*
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* Copyright (c) 2024 Qualcomm Technologies, Inc.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "camss.h"
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#include "camss-vfe.h"
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#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00)
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#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
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#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
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#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC)
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#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
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#define WM_CFG_EN BIT(0)
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#define WM_VIR_FRM_EN BIT(1)
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#define WM_CFG_MODE BIT(16)
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#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100)
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#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100)
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#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100)
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#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
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#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100)
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#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
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#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100)
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#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100)
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#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100)
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#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100)
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#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100)
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#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
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#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
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/*
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* Bus client mapping:
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*
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* Full VFE:
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* 23 = RDI0, 24 = RDI1, 25 = RDI2
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*
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* VFE LITE:
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* 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4
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*/
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#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
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static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
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{
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struct v4l2_pix_format_mplane *pix =
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&line->video_out.active_fmt.fmt.pix_mp;
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wm = RDI_WM(wm);
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/* no clock gating at bus input */
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writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
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writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
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writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
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vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
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writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
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vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
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writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
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vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
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writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
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/* no dropped frames, one irq per frame */
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writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
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writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
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writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
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writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
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writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
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writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
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writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
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}
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static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
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{
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wm = RDI_WM(wm);
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writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
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}
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static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
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struct vfe_line *line)
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{
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wm = RDI_WM(wm);
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writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
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dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n",
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wm, addr);
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}
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static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
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{
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int port_id = line_id;
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camss_reg_update(vfe->camss, vfe->id, port_id, false);
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}
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static inline void vfe_reg_update_clear(struct vfe_device *vfe,
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enum vfe_line_id line_id)
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{
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int port_id = line_id;
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camss_reg_update(vfe->camss, vfe->id, port_id, true);
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}
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static const struct camss_video_ops vfe_video_ops_780 = {
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.queue_buffer = vfe_queue_buffer_v2,
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.flush_buffers = vfe_flush_buffers,
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};
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static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
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{
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vfe->video_ops = vfe_video_ops_780;
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}
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static void vfe_global_reset(struct vfe_device *vfe)
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{
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vfe_isr_reset_ack(vfe);
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}
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static irqreturn_t vfe_isr(int irq, void *dev)
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{
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/* nop */
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return IRQ_HANDLED;
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}
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static int vfe_halt(struct vfe_device *vfe)
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{
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/* rely on vfe_disable_output() to stop the VFE */
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return 0;
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}
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const struct vfe_hw_ops vfe_ops_780 = {
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.global_reset = vfe_global_reset,
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.hw_version = vfe_hw_version,
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.isr = vfe_isr,
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.pm_domain_off = vfe_pm_domain_off,
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.pm_domain_on = vfe_pm_domain_on,
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.reg_update = vfe_reg_update,
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.reg_update_clear = vfe_reg_update_clear,
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.subdev_init = vfe_subdev_init,
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.vfe_disable = vfe_disable,
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.vfe_enable = vfe_enable_v2,
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.vfe_halt = vfe_halt,
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.vfe_wm_start = vfe_wm_start,
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.vfe_wm_stop = vfe_wm_stop,
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.vfe_buf_done = vfe_buf_done,
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.vfe_wm_update = vfe_wm_update,
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};
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@ -345,6 +345,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
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case CAMSS_8250:
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case CAMSS_8280XP:
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case CAMSS_845:
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case CAMSS_8550:
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switch (sink_code) {
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case MEDIA_BUS_FMT_YUYV8_1X16:
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{
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@ -1970,6 +1971,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
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case CAMSS_8250:
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case CAMSS_8280XP:
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case CAMSS_845:
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case CAMSS_8550:
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ret = 16;
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break;
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default:
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@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7;
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extern const struct vfe_hw_ops vfe_ops_4_8;
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extern const struct vfe_hw_ops vfe_ops_170;
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extern const struct vfe_hw_ops vfe_ops_480;
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extern const struct vfe_hw_ops vfe_ops_780;
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int vfe_get(struct vfe_device *vfe);
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void vfe_put(struct vfe_device *vfe);
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@ -2132,6 +2132,125 @@ static const struct camss_subdev_resources csid_res_8550[] = {
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}
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};
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static const struct camss_subdev_resources vfe_res_8550[] = {
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/* VFE0 */
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{
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.regulators = {},
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.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe0_fast_ahb",
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"vfe0", "cpas_vfe0", "camnoc_axi" },
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.clock_rate = { { 0 },
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{ 80000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 },
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{ 466000000, 594000000, 675000000, 785000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 } },
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.reg = { "vfe0" },
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.interrupt = { "vfe0" },
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.vfe = {
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.line_num = 3,
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.is_lite = false,
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.has_pd = true,
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.pd_name = "ife0",
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.hw_ops = &vfe_ops_780,
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.formats_rdi = &vfe_formats_rdi_845,
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.formats_pix = &vfe_formats_pix_845
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}
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},
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/* VFE1 */
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{
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.regulators = {},
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.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe1_fast_ahb",
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"vfe1", "cpas_vfe1", "camnoc_axi" },
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.clock_rate = { { 0 },
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{ 80000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 },
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{ 466000000, 594000000, 675000000, 785000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 } },
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.reg = { "vfe1" },
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.interrupt = { "vfe1" },
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.vfe = {
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.line_num = 3,
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.is_lite = false,
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.has_pd = true,
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.pd_name = "ife1",
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.hw_ops = &vfe_ops_780,
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.formats_rdi = &vfe_formats_rdi_845,
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.formats_pix = &vfe_formats_pix_845
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}
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},
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/* VFE2 */
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{
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.regulators = {},
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.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe2_fast_ahb",
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"vfe2", "cpas_vfe2", "camnoc_axi" },
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.clock_rate = { { 0 },
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{ 80000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 },
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{ 466000000, 594000000, 675000000, 785000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 } },
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.reg = { "vfe2" },
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.interrupt = { "vfe2" },
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.vfe = {
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.line_num = 3,
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.is_lite = false,
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.has_pd = true,
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.pd_name = "ife2",
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.hw_ops = &vfe_ops_780,
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.formats_rdi = &vfe_formats_rdi_845,
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.formats_pix = &vfe_formats_pix_845
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}
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},
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/* VFE3 lite */
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{
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.regulators = {},
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.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb",
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"vfe_lite", "cpas_ife_lite", "camnoc_axi" },
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.clock_rate = { { 0 },
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{ 80000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 },
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{ 400000000, 480000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 } },
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.reg = { "vfe_lite0" },
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.interrupt = { "vfe_lite0" },
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.vfe = {
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.line_num = 4,
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.is_lite = true,
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.hw_ops = &vfe_ops_780,
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.formats_rdi = &vfe_formats_rdi_845,
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.formats_pix = &vfe_formats_pix_845
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}
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},
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/* VFE4 lite */
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{
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.regulators = {},
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.clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb",
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"vfe_lite", "cpas_ife_lite", "camnoc_axi" },
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.clock_rate = { { 0 },
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{ 80000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 },
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{ 400000000, 480000000 },
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{ 300000000, 400000000 },
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{ 300000000, 400000000 } },
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.reg = { "vfe_lite1" },
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.interrupt = { "vfe_lite1" },
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.vfe = {
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.line_num = 4,
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.is_lite = true,
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.hw_ops = &vfe_ops_780,
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.formats_rdi = &vfe_formats_rdi_845,
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.formats_pix = &vfe_formats_pix_845
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}
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},
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};
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static const struct resources_icc icc_res_sm8550[] = {
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{
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.name = "ahb",
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@ -3186,11 +3305,13 @@ static const struct camss_resources sm8550_resources = {
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.pd_name = "top",
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.csiphy_res = csiphy_res_8550,
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.csid_res = csid_res_8550,
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.vfe_res = vfe_res_8550,
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.csid_wrapper_res = &csid_wrapper_res_sm8550,
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.icc_res = icc_res_sm8550,
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.icc_path_num = ARRAY_SIZE(icc_res_sm8550),
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.csiphy_num = ARRAY_SIZE(csiphy_res_8550),
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.csid_num = ARRAY_SIZE(csid_res_8550),
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.vfe_num = ARRAY_SIZE(vfe_res_8550),
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.link_entities = camss_link_entities
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};
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