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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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LoongArch: KVM: Add EIOINTC read and write functions
Add implementation of EIOINTC interrupt controller's address space read and write function simulation. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Xianglai Li
Huacai Chen
parent
2e8b9df826
commit
3956a52bc0
3 changed files with 771 additions and 3 deletions
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@ -20,9 +20,38 @@
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#define EIOINTC_BASE 0x1400
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#define EIOINTC_SIZE 0x900
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#define EIOINTC_NODETYPE_START 0xa0
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#define EIOINTC_NODETYPE_END 0xbf
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#define EIOINTC_IPMAP_START 0xc0
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#define EIOINTC_IPMAP_END 0xc7
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#define EIOINTC_ENABLE_START 0x200
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#define EIOINTC_ENABLE_END 0x21f
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#define EIOINTC_BOUNCE_START 0x280
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#define EIOINTC_BOUNCE_END 0x29f
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#define EIOINTC_ISR_START 0x300
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#define EIOINTC_ISR_END 0x31f
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#define EIOINTC_COREISR_START 0x400
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#define EIOINTC_COREISR_END 0x41f
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#define EIOINTC_COREMAP_START 0x800
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#define EIOINTC_COREMAP_END 0x8ff
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#define EIOINTC_VIRT_BASE (0x40000000)
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#define EIOINTC_VIRT_SIZE (0x1000)
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#define EIOINTC_VIRT_FEATURES (0x0)
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#define EIOINTC_HAS_VIRT_EXTENSION (0)
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#define EIOINTC_HAS_ENABLE_OPTION (1)
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#define EIOINTC_HAS_INT_ENCODE (2)
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#define EIOINTC_HAS_CPU_ENCODE (3)
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#define EIOINTC_VIRT_HAS_FEATURES ((1U << EIOINTC_HAS_VIRT_EXTENSION) \
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| (1U << EIOINTC_HAS_ENABLE_OPTION) \
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| (1U << EIOINTC_HAS_INT_ENCODE) \
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| (1U << EIOINTC_HAS_CPU_ENCODE))
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#define EIOINTC_VIRT_CONFIG (0x4)
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#define EIOINTC_ENABLE (1)
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#define EIOINTC_ENABLE_INT_ENCODE (2)
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#define EIOINTC_ENABLE_CPU_ENCODE (3)
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#define LOONGSON_IP_NUM 8
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struct loongarch_eiointc {
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@ -89,5 +118,6 @@ struct loongarch_eiointc {
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};
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int kvm_loongarch_register_eiointc_device(void);
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void eiointc_set_irq(struct loongarch_eiointc *s, int irq, int level);
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#endif /* __ASM_KVM_EIOINTC_H */
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@ -48,6 +48,8 @@ struct kvm_vm_stat {
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u64 hugepages;
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u64 ipi_read_exits;
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u64 ipi_write_exits;
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u64 eiointc_read_exits;
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u64 eiointc_write_exits;
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};
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struct kvm_vcpu_stat {
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@ -7,18 +7,700 @@
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#include <asm/kvm_vcpu.h>
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#include <linux/count_zeros.h>
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static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s)
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{
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int ipnum, cpu, irq_index, irq_mask, irq;
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for (irq = 0; irq < EIOINTC_IRQS; irq++) {
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ipnum = s->ipmap.reg_u8[irq / 32];
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if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) {
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ipnum = count_trailing_zeros(ipnum);
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ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0;
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}
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irq_index = irq / 32;
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irq_mask = BIT(irq & 0x1f);
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cpu = s->coremap.reg_u8[irq];
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if (!!(s->coreisr.reg_u32[cpu][irq_index] & irq_mask))
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set_bit(irq, s->sw_coreisr[cpu][ipnum]);
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else
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clear_bit(irq, s->sw_coreisr[cpu][ipnum]);
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}
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}
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static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int level)
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{
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int ipnum, cpu, found, irq_index, irq_mask;
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struct kvm_vcpu *vcpu;
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struct kvm_interrupt vcpu_irq;
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ipnum = s->ipmap.reg_u8[irq / 32];
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if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) {
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ipnum = count_trailing_zeros(ipnum);
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ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0;
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}
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cpu = s->sw_coremap[irq];
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vcpu = kvm_get_vcpu(s->kvm, cpu);
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irq_index = irq / 32;
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irq_mask = BIT(irq & 0x1f);
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if (level) {
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/* if not enable return false */
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if (((s->enable.reg_u32[irq_index]) & irq_mask) == 0)
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return;
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s->coreisr.reg_u32[cpu][irq_index] |= irq_mask;
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found = find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS);
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set_bit(irq, s->sw_coreisr[cpu][ipnum]);
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} else {
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s->coreisr.reg_u32[cpu][irq_index] &= ~irq_mask;
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clear_bit(irq, s->sw_coreisr[cpu][ipnum]);
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found = find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS);
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}
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if (found < EIOINTC_IRQS)
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return; /* other irq is handling, needn't update parent irq */
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vcpu_irq.irq = level ? (INT_HWI0 + ipnum) : -(INT_HWI0 + ipnum);
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kvm_vcpu_ioctl_interrupt(vcpu, &vcpu_irq);
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}
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static inline void eiointc_update_sw_coremap(struct loongarch_eiointc *s,
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int irq, void *pvalue, u32 len, bool notify)
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{
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int i, cpu;
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u64 val = *(u64 *)pvalue;
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for (i = 0; i < len; i++) {
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cpu = val & 0xff;
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val = val >> 8;
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if (!(s->status & BIT(EIOINTC_ENABLE_CPU_ENCODE))) {
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cpu = ffs(cpu) - 1;
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cpu = (cpu >= 4) ? 0 : cpu;
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}
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if (s->sw_coremap[irq + i] == cpu)
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continue;
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if (notify && test_bit(irq + i, (unsigned long *)s->isr.reg_u8)) {
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/* lower irq at old cpu and raise irq at new cpu */
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eiointc_update_irq(s, irq + i, 0);
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s->sw_coremap[irq + i] = cpu;
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eiointc_update_irq(s, irq + i, 1);
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} else {
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s->sw_coremap[irq + i] = cpu;
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}
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}
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}
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void eiointc_set_irq(struct loongarch_eiointc *s, int irq, int level)
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{
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unsigned long flags;
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unsigned long *isr = (unsigned long *)s->isr.reg_u8;
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level ? set_bit(irq, isr) : clear_bit(irq, isr);
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spin_lock_irqsave(&s->lock, flags);
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eiointc_update_irq(s, irq, level);
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spin_unlock_irqrestore(&s->lock, flags);
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}
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static inline void eiointc_enable_irq(struct kvm_vcpu *vcpu,
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struct loongarch_eiointc *s, int index, u8 mask, int level)
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{
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u8 val;
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int irq;
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val = mask & s->isr.reg_u8[index];
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irq = ffs(val);
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while (irq != 0) {
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/*
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* enable bit change from 0 to 1,
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* need to update irq by pending bits
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*/
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eiointc_update_irq(s, irq - 1 + index * 8, level);
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val &= ~BIT(irq - 1);
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irq = ffs(val);
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}
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}
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static int loongarch_eiointc_readb(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u8 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = offset - EIOINTC_NODETYPE_START;
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data = s->nodetype.reg_u8[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = offset - EIOINTC_IPMAP_START;
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data = s->ipmap.reg_u8[index];
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = offset - EIOINTC_ENABLE_START;
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data = s->enable.reg_u8[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = offset - EIOINTC_BOUNCE_START;
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data = s->bounce.reg_u8[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = offset - EIOINTC_COREISR_START;
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data = s->coreisr.reg_u8[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = offset - EIOINTC_COREMAP_START;
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data = s->coremap.reg_u8[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u8 *)val = data;
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return ret;
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}
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static int loongarch_eiointc_readw(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u16 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 1;
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data = s->nodetype.reg_u16[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = (offset - EIOINTC_IPMAP_START) >> 1;
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data = s->ipmap.reg_u16[index];
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 1;
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data = s->enable.reg_u16[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = (offset - EIOINTC_BOUNCE_START) >> 1;
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data = s->bounce.reg_u16[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START) >> 1;
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data = s->coreisr.reg_u16[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = (offset - EIOINTC_COREMAP_START) >> 1;
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data = s->coremap.reg_u16[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u16 *)val = data;
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return ret;
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}
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static int loongarch_eiointc_readl(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u32 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 2;
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data = s->nodetype.reg_u32[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = (offset - EIOINTC_IPMAP_START) >> 2;
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data = s->ipmap.reg_u32[index];
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 2;
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data = s->enable.reg_u32[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = (offset - EIOINTC_BOUNCE_START) >> 2;
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data = s->bounce.reg_u32[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START) >> 2;
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data = s->coreisr.reg_u32[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = (offset - EIOINTC_COREMAP_START) >> 2;
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data = s->coremap.reg_u32[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u32 *)val = data;
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return ret;
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}
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static int loongarch_eiointc_readq(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u64 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 3;
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data = s->nodetype.reg_u64[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = (offset - EIOINTC_IPMAP_START) >> 3;
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data = s->ipmap.reg_u64;
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 3;
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data = s->enable.reg_u64[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = (offset - EIOINTC_BOUNCE_START) >> 3;
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data = s->bounce.reg_u64[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START) >> 3;
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data = s->coreisr.reg_u64[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = (offset - EIOINTC_COREMAP_START) >> 3;
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data = s->coremap.reg_u64[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u64 *)val = data;
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return ret;
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}
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static int kvm_eiointc_read(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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return 0;
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int ret = -EINVAL;
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unsigned long flags;
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struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
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if (!eiointc) {
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kvm_err("%s: eiointc irqchip not valid!\n", __func__);
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return -EINVAL;
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}
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vcpu->kvm->stat.eiointc_read_exits++;
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spin_lock_irqsave(&eiointc->lock, flags);
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switch (len) {
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case 1:
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ret = loongarch_eiointc_readb(vcpu, eiointc, addr, len, val);
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break;
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case 2:
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ret = loongarch_eiointc_readw(vcpu, eiointc, addr, len, val);
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break;
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case 4:
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ret = loongarch_eiointc_readl(vcpu, eiointc, addr, len, val);
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break;
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case 8:
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ret = loongarch_eiointc_readq(vcpu, eiointc, addr, len, val);
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break;
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default:
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WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n",
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__func__, addr, len);
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}
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spin_unlock_irqrestore(&eiointc->lock, flags);
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return ret;
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}
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static int loongarch_eiointc_writeb(struct kvm_vcpu *vcpu,
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struct loongarch_eiointc *s,
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gpa_t addr, int len, const void *val)
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{
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int index, irq, bits, ret = 0;
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u8 cpu;
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u8 data, old_data;
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u8 coreisr, old_coreisr;
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gpa_t offset;
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data = *(u8 *)val;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START);
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s->nodetype.reg_u8[index] = data;
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of irqchip driver, need not update upper irq level
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*/
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index = (offset - EIOINTC_IPMAP_START);
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s->ipmap.reg_u8[index] = data;
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
||||
index = (offset - EIOINTC_ENABLE_START);
|
||||
old_data = s->enable.reg_u8[index];
|
||||
s->enable.reg_u8[index] = data;
|
||||
/*
|
||||
* 1: enable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = s->enable.reg_u8[index] & ~old_data & s->isr.reg_u8[index];
|
||||
eiointc_enable_irq(vcpu, s, index, data, 1);
|
||||
/*
|
||||
* 0: disable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = ~s->enable.reg_u8[index] & old_data & s->isr.reg_u8[index];
|
||||
eiointc_enable_irq(vcpu, s, index, data, 0);
|
||||
break;
|
||||
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
||||
/* do not emulate hw bounced irq routing */
|
||||
index = offset - EIOINTC_BOUNCE_START;
|
||||
s->bounce.reg_u8[index] = data;
|
||||
break;
|
||||
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
||||
index = (offset - EIOINTC_COREISR_START);
|
||||
/* use attrs to get current cpu index */
|
||||
cpu = vcpu->vcpu_id;
|
||||
coreisr = data;
|
||||
old_coreisr = s->coreisr.reg_u8[cpu][index];
|
||||
/* write 1 to clear interrupt */
|
||||
s->coreisr.reg_u8[cpu][index] = old_coreisr & ~coreisr;
|
||||
coreisr &= old_coreisr;
|
||||
bits = sizeof(data) * 8;
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
while (irq < bits) {
|
||||
eiointc_update_irq(s, irq + index * bits, 0);
|
||||
bitmap_clear((void *)&coreisr, irq, 1);
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
||||
irq = offset - EIOINTC_COREMAP_START;
|
||||
index = irq;
|
||||
s->coremap.reg_u8[index] = data;
|
||||
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_eiointc_writew(struct kvm_vcpu *vcpu,
|
||||
struct loongarch_eiointc *s,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
int i, index, irq, bits, ret = 0;
|
||||
u8 cpu;
|
||||
u16 data, old_data;
|
||||
u16 coreisr, old_coreisr;
|
||||
gpa_t offset;
|
||||
|
||||
data = *(u16 *)val;
|
||||
offset = addr - EIOINTC_BASE;
|
||||
|
||||
switch (offset) {
|
||||
case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
|
||||
index = (offset - EIOINTC_NODETYPE_START) >> 1;
|
||||
s->nodetype.reg_u16[index] = data;
|
||||
break;
|
||||
case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
|
||||
/*
|
||||
* ipmap cannot be set at runtime, can be set only at the beginning
|
||||
* of irqchip driver, need not update upper irq level
|
||||
*/
|
||||
index = (offset - EIOINTC_IPMAP_START) >> 1;
|
||||
s->ipmap.reg_u16[index] = data;
|
||||
break;
|
||||
case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
||||
index = (offset - EIOINTC_ENABLE_START) >> 1;
|
||||
old_data = s->enable.reg_u32[index];
|
||||
s->enable.reg_u16[index] = data;
|
||||
/*
|
||||
* 1: enable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = s->enable.reg_u16[index] & ~old_data & s->isr.reg_u16[index];
|
||||
index = index << 1;
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
u8 mask = (data >> (i * 8)) & 0xff;
|
||||
eiointc_enable_irq(vcpu, s, index + i, mask, 1);
|
||||
}
|
||||
/*
|
||||
* 0: disable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = ~s->enable.reg_u16[index] & old_data & s->isr.reg_u16[index];
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
u8 mask = (data >> (i * 8)) & 0xff;
|
||||
eiointc_enable_irq(vcpu, s, index, mask, 0);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
||||
/* do not emulate hw bounced irq routing */
|
||||
index = (offset - EIOINTC_BOUNCE_START) >> 1;
|
||||
s->bounce.reg_u16[index] = data;
|
||||
break;
|
||||
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
||||
index = (offset - EIOINTC_COREISR_START) >> 1;
|
||||
/* use attrs to get current cpu index */
|
||||
cpu = vcpu->vcpu_id;
|
||||
coreisr = data;
|
||||
old_coreisr = s->coreisr.reg_u16[cpu][index];
|
||||
/* write 1 to clear interrupt */
|
||||
s->coreisr.reg_u16[cpu][index] = old_coreisr & ~coreisr;
|
||||
coreisr &= old_coreisr;
|
||||
bits = sizeof(data) * 8;
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
while (irq < bits) {
|
||||
eiointc_update_irq(s, irq + index * bits, 0);
|
||||
bitmap_clear((void *)&coreisr, irq, 1);
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
||||
irq = offset - EIOINTC_COREMAP_START;
|
||||
index = irq >> 1;
|
||||
s->coremap.reg_u16[index] = data;
|
||||
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_eiointc_writel(struct kvm_vcpu *vcpu,
|
||||
struct loongarch_eiointc *s,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
int i, index, irq, bits, ret = 0;
|
||||
u8 cpu;
|
||||
u32 data, old_data;
|
||||
u32 coreisr, old_coreisr;
|
||||
gpa_t offset;
|
||||
|
||||
data = *(u32 *)val;
|
||||
offset = addr - EIOINTC_BASE;
|
||||
|
||||
switch (offset) {
|
||||
case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
|
||||
index = (offset - EIOINTC_NODETYPE_START) >> 2;
|
||||
s->nodetype.reg_u32[index] = data;
|
||||
break;
|
||||
case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
|
||||
/*
|
||||
* ipmap cannot be set at runtime, can be set only at the beginning
|
||||
* of irqchip driver, need not update upper irq level
|
||||
*/
|
||||
index = (offset - EIOINTC_IPMAP_START) >> 2;
|
||||
s->ipmap.reg_u32[index] = data;
|
||||
break;
|
||||
case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
||||
index = (offset - EIOINTC_ENABLE_START) >> 2;
|
||||
old_data = s->enable.reg_u32[index];
|
||||
s->enable.reg_u32[index] = data;
|
||||
/*
|
||||
* 1: enable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = s->enable.reg_u32[index] & ~old_data & s->isr.reg_u32[index];
|
||||
index = index << 2;
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
u8 mask = (data >> (i * 8)) & 0xff;
|
||||
eiointc_enable_irq(vcpu, s, index + i, mask, 1);
|
||||
}
|
||||
/*
|
||||
* 0: disable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = ~s->enable.reg_u32[index] & old_data & s->isr.reg_u32[index];
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
u8 mask = (data >> (i * 8)) & 0xff;
|
||||
eiointc_enable_irq(vcpu, s, index, mask, 0);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
||||
/* do not emulate hw bounced irq routing */
|
||||
index = (offset - EIOINTC_BOUNCE_START) >> 2;
|
||||
s->bounce.reg_u32[index] = data;
|
||||
break;
|
||||
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
||||
index = (offset - EIOINTC_COREISR_START) >> 2;
|
||||
/* use attrs to get current cpu index */
|
||||
cpu = vcpu->vcpu_id;
|
||||
coreisr = data;
|
||||
old_coreisr = s->coreisr.reg_u32[cpu][index];
|
||||
/* write 1 to clear interrupt */
|
||||
s->coreisr.reg_u32[cpu][index] = old_coreisr & ~coreisr;
|
||||
coreisr &= old_coreisr;
|
||||
bits = sizeof(data) * 8;
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
while (irq < bits) {
|
||||
eiointc_update_irq(s, irq + index * bits, 0);
|
||||
bitmap_clear((void *)&coreisr, irq, 1);
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
||||
irq = offset - EIOINTC_COREMAP_START;
|
||||
index = irq >> 2;
|
||||
s->coremap.reg_u32[index] = data;
|
||||
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_eiointc_writeq(struct kvm_vcpu *vcpu,
|
||||
struct loongarch_eiointc *s,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
int i, index, irq, bits, ret = 0;
|
||||
u8 cpu;
|
||||
u64 data, old_data;
|
||||
u64 coreisr, old_coreisr;
|
||||
gpa_t offset;
|
||||
|
||||
data = *(u64 *)val;
|
||||
offset = addr - EIOINTC_BASE;
|
||||
|
||||
switch (offset) {
|
||||
case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
|
||||
index = (offset - EIOINTC_NODETYPE_START) >> 3;
|
||||
s->nodetype.reg_u64[index] = data;
|
||||
break;
|
||||
case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
|
||||
/*
|
||||
* ipmap cannot be set at runtime, can be set only at the beginning
|
||||
* of irqchip driver, need not update upper irq level
|
||||
*/
|
||||
index = (offset - EIOINTC_IPMAP_START) >> 3;
|
||||
s->ipmap.reg_u64 = data;
|
||||
break;
|
||||
case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
||||
index = (offset - EIOINTC_ENABLE_START) >> 3;
|
||||
old_data = s->enable.reg_u64[index];
|
||||
s->enable.reg_u64[index] = data;
|
||||
/*
|
||||
* 1: enable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = s->enable.reg_u64[index] & ~old_data & s->isr.reg_u64[index];
|
||||
index = index << 3;
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
u8 mask = (data >> (i * 8)) & 0xff;
|
||||
eiointc_enable_irq(vcpu, s, index + i, mask, 1);
|
||||
}
|
||||
/*
|
||||
* 0: disable irq.
|
||||
* update irq when isr is set.
|
||||
*/
|
||||
data = ~s->enable.reg_u64[index] & old_data & s->isr.reg_u64[index];
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
u8 mask = (data >> (i * 8)) & 0xff;
|
||||
eiointc_enable_irq(vcpu, s, index, mask, 0);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
||||
/* do not emulate hw bounced irq routing */
|
||||
index = (offset - EIOINTC_BOUNCE_START) >> 3;
|
||||
s->bounce.reg_u64[index] = data;
|
||||
break;
|
||||
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
||||
index = (offset - EIOINTC_COREISR_START) >> 3;
|
||||
/* use attrs to get current cpu index */
|
||||
cpu = vcpu->vcpu_id;
|
||||
coreisr = data;
|
||||
old_coreisr = s->coreisr.reg_u64[cpu][index];
|
||||
/* write 1 to clear interrupt */
|
||||
s->coreisr.reg_u64[cpu][index] = old_coreisr & ~coreisr;
|
||||
coreisr &= old_coreisr;
|
||||
bits = sizeof(data) * 8;
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
while (irq < bits) {
|
||||
eiointc_update_irq(s, irq + index * bits, 0);
|
||||
bitmap_clear((void *)&coreisr, irq, 1);
|
||||
irq = find_first_bit((void *)&coreisr, bits);
|
||||
}
|
||||
break;
|
||||
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
||||
irq = offset - EIOINTC_COREMAP_START;
|
||||
index = irq >> 3;
|
||||
s->coremap.reg_u64[index] = data;
|
||||
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int kvm_eiointc_write(struct kvm_vcpu *vcpu,
|
||||
struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
return 0;
|
||||
int ret = -EINVAL;
|
||||
unsigned long flags;
|
||||
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
|
||||
|
||||
if (!eiointc) {
|
||||
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
vcpu->kvm->stat.eiointc_write_exits++;
|
||||
spin_lock_irqsave(&eiointc->lock, flags);
|
||||
switch (len) {
|
||||
case 1:
|
||||
ret = loongarch_eiointc_writeb(vcpu, eiointc, addr, len, val);
|
||||
break;
|
||||
case 2:
|
||||
ret = loongarch_eiointc_writew(vcpu, eiointc, addr, len, val);
|
||||
break;
|
||||
case 4:
|
||||
ret = loongarch_eiointc_writel(vcpu, eiointc, addr, len, val);
|
||||
break;
|
||||
case 8:
|
||||
ret = loongarch_eiointc_writeq(vcpu, eiointc, addr, len, val);
|
||||
break;
|
||||
default:
|
||||
WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n",
|
||||
__func__, addr, len);
|
||||
}
|
||||
spin_unlock_irqrestore(&eiointc->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct kvm_io_device_ops kvm_eiointc_ops = {
|
||||
|
|
@ -30,6 +712,29 @@ static int kvm_eiointc_virt_read(struct kvm_vcpu *vcpu,
|
|||
struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 *data = val;
|
||||
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
|
||||
|
||||
if (!eiointc) {
|
||||
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
addr -= EIOINTC_VIRT_BASE;
|
||||
spin_lock_irqsave(&eiointc->lock, flags);
|
||||
switch (addr) {
|
||||
case EIOINTC_VIRT_FEATURES:
|
||||
*data = eiointc->features;
|
||||
break;
|
||||
case EIOINTC_VIRT_CONFIG:
|
||||
*data = eiointc->status;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
spin_unlock_irqrestore(&eiointc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -37,7 +742,38 @@ static int kvm_eiointc_virt_write(struct kvm_vcpu *vcpu,
|
|||
struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
return 0;
|
||||
int ret = 0;
|
||||
unsigned long flags;
|
||||
u32 value = *(u32 *)val;
|
||||
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
|
||||
|
||||
if (!eiointc) {
|
||||
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
addr -= EIOINTC_VIRT_BASE;
|
||||
spin_lock_irqsave(&eiointc->lock, flags);
|
||||
switch (addr) {
|
||||
case EIOINTC_VIRT_FEATURES:
|
||||
ret = -EPERM;
|
||||
break;
|
||||
case EIOINTC_VIRT_CONFIG:
|
||||
/*
|
||||
* eiointc features can only be set at disabled status
|
||||
*/
|
||||
if ((eiointc->status & BIT(EIOINTC_ENABLE)) && value) {
|
||||
ret = -EPERM;
|
||||
break;
|
||||
}
|
||||
eiointc->status = value & eiointc->features;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
spin_unlock_irqrestore(&eiointc->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct kvm_io_device_ops kvm_eiointc_virt_ops = {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue