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arm64: zynqmp: Add mali-400 gpu node for zynqmp

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Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Parth Gajjar 2023-03-21 00:06:19 -07:00 • committed by Michal Simek
parent 80550562f6
commit 37e7894910
11 changed files with 51 additions and 0 deletions
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4
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View file

@ -95,6 +95,10 @@
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gpu {
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

4
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
View file

@ -287,3 +287,7 @@
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 173 */
};
&gpu {
status = "okay";
};

3
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View file

@ -108,6 +108,9 @@
pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
View file

@ -152,6 +152,10 @@
status = "okay";
};
&gpu {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View file

@ -161,6 +161,10 @@
"", "", "", "";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "gpio";

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View file

@ -216,6 +216,10 @@
pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View file

@ -122,6 +122,10 @@
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
View file

@ -127,6 +127,10 @@
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View file

@ -227,6 +227,10 @@
pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View file

@ -187,6 +187,10 @@
pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;

12
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file

@ -411,6 +411,18 @@
interrupts = <1 9 0xf04>;
};
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>,
<0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
/* LPDDMA default allows only secured access. inorder to enable
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.