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More Qualcomm driver updates for v6.5

Browse source 
The detection of split/non-split firmware files in the MDT loader is
 corrected. The Geni driver is updated to not enable unused interrupts,
 in some configurations. The count unit for MSM8998 in BWMON is corrected.
 RPM master stats driver is corrected to check for the right return value
 of devm_ioremap().
 
 Support for socinfo version 18 and 19 are aded, and IPQ5300 is added to
 the list of platforms.
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Merge tag 'qcom-drivers-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

More Qualcomm driver updates for v6.5

The detection of split/non-split firmware files in the MDT loader is
corrected. The Geni driver is updated to not enable unused interrupts,
in some configurations. The count unit for MSM8998 in BWMON is corrected.
RPM master stats driver is corrected to check for the right return value
of devm_ioremap().

Support for socinfo version 18 and 19 are aded, and IPQ5300 is added to
the list of platforms.

* tag 'qcom-drivers-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer
  dt-bindings: sram: qcom,imem: document qdu1000
  soc: qcom: icc-bwmon: Fix MSM8998 count unit
  dt-bindings: soc: qcom,rpmh-rsc: Require power-domains
  soc: qcom: socinfo: Add Soc ID for IPQ5300
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
  soc: qcom: Fix a IS_ERR() vs NULL bug in probe
  soc: qcom: socinfo: Add support for new fields in revision 19
  soc: qcom: socinfo: Add support for new fields in revision 18
  dt-bindings: firmware: scm: Add compatible for SDX75
  soc: qcom: mdt_loader: Fix split image detection

Link: https://lore.kernel.org/r/20230615163104.1461905-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-21 22:15:10 +02:00
commit 37d1fc51dd
10 changed files with 54 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View file

@ -51,6 +51,7 @@ properties:
- qcom,scm-sdm845
- qcom,scm-sdx55
- qcom,scm-sdx65
- qcom,scm-sdx75
- qcom,scm-sm6115
- qcom,scm-sm6125
- qcom,scm-sm6350

2
Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
View file

@ -124,6 +124,7 @@ required:
- qcom,tcs-offset
- reg
- reg-names
- power-domains
additionalProperties: false
@ -179,6 +180,7 @@ examples:
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
power-domains = <&CLUSTER_PD>;
};
- |

1
Documentation/devicetree/bindings/sram/qcom,imem.yaml
View file

@ -21,6 +21,7 @@ properties:
- qcom,msm8226-imem
- qcom,msm8974-imem
- qcom,qcs404-imem
- qcom,qdu1000-imem
- qcom,sc7180-imem
- qcom,sc7280-imem
- qcom,sdm630-imem

2
drivers/soc/qcom/icc-bwmon.c
View file

@ -806,7 +806,7 @@ static int bwmon_remove(struct platform_device *pdev)
static const struct icc_bwmon_data msm8998_bwmon_data = {
.sample_ms = 4,
.count_unit_kb = 64,
.count_unit_kb = 1024,
.default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */
.default_medbw_kbps = 512 * 1024, /* 512 MBps */
.default_lowbw_kbps = 0,

8
drivers/soc/qcom/mdt_loader.c
View file

@ -275,6 +275,14 @@ static bool qcom_mdt_bins_are_split(const struct firmware *fw, const char *fw_na
phdrs = (struct elf32_phdr *)(ehdr + 1);
for (i = 0; i < ehdr->e_phnum; i++) {
/*
* The size of the MDT file is not padded to include any
* zero-sized segments at the end. Ignore these, as they should
* not affect the decision about image being split or not.
*/
if (!phdrs[i].p_filesz)
continue;
seg_start = phdrs[i].p_offset;
seg_end = phdrs[i].p_offset + phdrs[i].p_filesz;
if (seg_start > fw->size || seg_end > fw->size)

28
drivers/soc/qcom/qcom-geni-se.c
View file

@ -281,27 +281,14 @@ static void geni_se_select_fifo_mode(struct geni_se *se)
geni_se_irq_clear(se);
/*
* The RX path for the UART is asynchronous and so needs more
* complex logic for enabling / disabling its interrupts.
*
* Specific notes:
* - The done and TX-related interrupts are managed manually.
* - We don't RX from the main sequencer (we use the secondary) so
* we don't need the RX-related interrupts enabled in the main
* sequencer for UART.
*/
/* UART driver manages enabling / disabling interrupts internally */
if (proto != GENI_SE_UART) {
/* Non-UART use only primary sequencer so dont bother about S_IRQ */
val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
if (val != val_old)
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
val |= S_CMD_DONE_EN;
if (val != val_old)
writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
}
val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
@ -317,17 +304,14 @@ static void geni_se_select_dma_mode(struct geni_se *se)
geni_se_irq_clear(se);
/* UART driver manages enabling / disabling interrupts internally */
if (proto != GENI_SE_UART) {
/* Non-UART use only primary sequencer so dont bother about S_IRQ */
val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
if (val != val_old)
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
val &= ~S_CMD_DONE_EN;
if (val != val_old)
writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
}
val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
@ -344,10 +328,6 @@ static void geni_se_select_gpi_mode(struct geni_se *se)
writel(0, se->base + SE_IRQ_EN);
val = readl(se->base + SE_GENI_S_IRQ_EN);
val &= ~S_CMD_DONE_EN;
writel(val, se->base + SE_GENI_S_IRQ_EN);
val = readl(se->base + SE_GENI_M_IRQ_EN);
val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);

2
drivers/soc/qcom/rpm_master_stats.c
View file

@ -105,7 +105,7 @@ static int master_stats_probe(struct platform_device *pdev)
}
data[i].base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(data[i].base)) {
if (!data[i].base) {
debugfs_remove_recursive(root);
return dev_err_probe(dev, -EINVAL,
"Could not map the MSG RAM slice idx %d!\n", i);

34
drivers/soc/qcom/socinfo.c
View file

@ -133,12 +133,15 @@ struct socinfo_params {
u32 nproduct_id;
u32 num_clusters;
u32 ncluster_array_offset;
u32 num_defective_parts;
u32 ndefective_parts_array_offset;
u32 num_subset_parts;
u32 nsubset_parts_array_offset;
u32 nmodem_supported;
u32 feature_code;
u32 pcode;
u32 oem_variant;
u32 num_func_clusters;
u32 boot_cluster;
u32 boot_core;
};
struct smem_image_version {
@ -411,6 +414,7 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(IPQ5322) },
{ qcom_board_id(IPQ5312) },
{ qcom_board_id(IPQ5302) },
{ qcom_board_id(IPQ5300) },
};
static const char *socinfo_machine(struct device *dev, unsigned int id)
@ -565,6 +569,19 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
&qcom_socinfo->info.fmt);
switch (qcom_socinfo->info.fmt) {
case SOCINFO_VERSION(0, 19):
qcom_socinfo->info.num_func_clusters = __le32_to_cpu(info->num_func_clusters);
qcom_socinfo->info.boot_cluster = __le32_to_cpu(info->boot_cluster);
qcom_socinfo->info.boot_core = __le32_to_cpu(info->boot_core);
debugfs_create_u32("num_func_clusters", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.num_func_clusters);
debugfs_create_u32("boot_cluster", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.boot_cluster);
debugfs_create_u32("boot_core", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.boot_core);
fallthrough;
case SOCINFO_VERSION(0, 18):
case SOCINFO_VERSION(0, 17):
qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant);
debugfs_create_u32("oem_variant", 0444, qcom_socinfo->dbg_root,
@ -588,17 +605,18 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
case SOCINFO_VERSION(0, 14):
qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
qcom_socinfo->info.num_subset_parts = __le32_to_cpu(info->num_subset_parts);
qcom_socinfo->info.nsubset_parts_array_offset =
__le32_to_cpu(info->nsubset_parts_array_offset);
debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.num_clusters);
debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.ncluster_array_offset);
debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.num_defective_parts);
debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.ndefective_parts_array_offset);
debugfs_create_u32("num_subset_parts", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.num_subset_parts);
debugfs_create_u32("nsubset_parts_array_offset", 0444, qcom_socinfo->dbg_root,
&qcom_socinfo->info.nsubset_parts_array_offset);
fallthrough;
case SOCINFO_VERSION(0, 13):
qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);

1
include/dt-bindings/arm/qcom,ids.h
View file

@ -258,6 +258,7 @@
#define QCOM_ID_IPQ5322 593
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
#define QCOM_ID_IPQ5300 624
/*
* The board type and revision information, used by Qualcomm bootloaders and

11
include/linux/soc/qcom/socinfo.h
View file

@ -54,8 +54,8 @@ struct socinfo {
/* Version 14 */
__le32 num_clusters;
__le32 ncluster_array_offset;
__le32 num_defective_parts;
__le32 ndefective_parts_array_offset;
__le32 num_subset_parts;
__le32 nsubset_parts_array_offset;
/* Version 15 */
__le32 nmodem_supported;
/* Version 16 */
@ -65,6 +65,13 @@ struct socinfo {
__le32 nnum_partname_mapping;
/* Version 17 */
__le32 oem_variant;
/* Version 18 */
__le32 num_kvps;
__le32 kvps_offset;
/* Version 19 */
__le32 num_func_clusters;
__le32 boot_cluster;
__le32 boot_core;
};
#endif