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irqchip/gic-v3-its: Reduce minimum LPI allocation to 1 for PCI devices
Allocating a minimum of 32 LPIs per PCI device, let's reduce it to be just 1, as most devices do not need that many interrupts. We still have to special-case DevID 0, as there is plenty of broken HW around where the PCI RID is not presented as a DevID to the ITS, and all the devices are presented as DevID 0. In this case, we keep the 32 minimal allocation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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12b2905af1
commit
30800b3a1f
1 changed files with 11 additions and 3 deletions
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@ -66,7 +66,7 @@ static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
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{
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{
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struct pci_dev *pdev, *alias_dev;
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struct pci_dev *pdev, *alias_dev;
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struct msi_domain_info *msi_info;
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struct msi_domain_info *msi_info;
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int alias_count = 0;
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int alias_count = 0, minnvec = 1;
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if (!dev_is_pci(dev))
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if (!dev_is_pci(dev))
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return -EINVAL;
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return -EINVAL;
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@ -86,9 +86,17 @@ static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
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/* ITS specific DeviceID, as the core ITS ignores dev. */
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/* ITS specific DeviceID, as the core ITS ignores dev. */
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info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev);
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info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev);
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/* Allocate at least 32 MSIs, and always as a power of 2 */
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/*
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* Always allocate a power of 2, and special case device 0 for
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* broken systems where the DevID is not wired (and all devices
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* appear as DevID 0). For that reason, we generously allocate a
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* minimum of 32 MSIs for DevID 0. If you want more because all
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* your devices are aliasing to DevID 0, consider fixing your HW.
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*/
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nvec = max(nvec, alias_count);
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nvec = max(nvec, alias_count);
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nvec = max_t(int, 32, roundup_pow_of_two(nvec));
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if (!info->scratchpad[0].ul)
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minnvec = 32;
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nvec = max_t(int, minnvec, roundup_pow_of_two(nvec));
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return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info);
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return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info);
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}
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}
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