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arm64: dts: qcom: sc7280: Remove CTS/RTS configuration

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For IDP variant, GPIO 20/21 is used by camera use case and camera
driver is not able acquire these GPIOs as it is acquired by UART5
driver as RTS/CTS pin.

UART5 is designed for debug UART for all the board variants of the
sc7280 chipset and RTS/CTS configuration is not required for debug
uart usecase.

Remove CTS/RTS configuration for UART5 instance and change compatible
string to debug UART.

Remove overwriting compatible property from individual target specific
file as it is not required.

Fixes: 38cd93f413 ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node")
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20240424075853.11445-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Viken Dadhaniya 2024-04-24 13:28:53 +05:30 • committed by Bjorn Andersson
parent fbc7a70b2c
commit 2b96407b8f
6 changed files with 2 additions and 17 deletions
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1
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View file

@ -864,7 +864,6 @@
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};

1
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View file

@ -658,7 +658,6 @@
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};

1
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View file

@ -648,7 +648,6 @@
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};

1
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View file

@ -495,7 +495,6 @@
};
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};

1
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View file

@ -427,7 +427,6 @@
};
uart_dbg: &uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};

14
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file

@ -1440,12 +1440,12 @@
};
uart5: serial@994000 {
compatible = "qcom,geni-uart";
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
@ -5407,16 +5407,6 @@
function = "qup04";
};
qup_uart5_cts: qup-uart5-cts-state {
pins = "gpio20";
function = "qup05";
};
qup_uart5_rts: qup-uart5-rts-state {
pins = "gpio21";
function = "qup05";
};
qup_uart5_tx: qup-uart5-tx-state {
pins = "gpio22";
function = "qup05";