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[ARM] 4583/1: ARMv7: Add VFPv3 support
This patch adds the support for VFPv3 (the kernel currently supports VFPv2). The main difference is 32 double registers (compared to 16). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas
Russell King
parent
c98929c07a
commit
25ebee020b
7 changed files with 60 additions and 12 deletions
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@ -951,7 +951,7 @@ config FPE_FASTFPE
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config VFP
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bool "VFP-format floating point maths"
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depends on CPU_V6 || CPU_ARM926T
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depends on CPU_V6 || CPU_ARM926T || CPU_V7
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help
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Say Y to include VFP support code in the kernel. This is needed
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if your hardware includes a VFP unit.
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@ -961,6 +961,11 @@ config VFP
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Say N if your target does not have VFP hardware.
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config VFPv3
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bool
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depends on VFP
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default y if CPU_V7
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endmenu
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menu "Userspace binary formats"
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@ -265,7 +265,11 @@ struct vfp_double {
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* which returns (double)0.0. This is useful for the compare with
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* zero instructions.
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*/
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#ifdef CONFIG_VFPv3
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#define VFP_REG_ZERO 32
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#else
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#define VFP_REG_ZERO 16
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#endif
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extern u64 vfp_get_double(unsigned int reg);
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extern void vfp_put_double(u64 val, unsigned int reg);
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@ -99,12 +99,12 @@ vfp_support_entry:
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DBGSTR1 "save old state %p", r4
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cmp r4, #0
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beq no_old_VFP_process
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VFPFSTMIA r4, r5 @ save the working registers
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VFPFMRX r5, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present)
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VFPFSTMIA r4 @ save the working registers
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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@ and point r4 at the word at the
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@ start of the register dump
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@ -114,7 +114,7 @@ no_old_VFP_process:
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DBGSTR1 "load state %p", r10
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str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
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@ Load the saved state back into the VFP
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VFPFLDMIA r10 @ reload the working registers while
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VFPFLDMIA r10, r5 @ reload the working registers while
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@ FPEXC is in a safe state
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ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
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tst r1, #FPEXC_EX @ is there additional state to restore?
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@ -174,12 +174,12 @@ vfp_save_state:
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@ r0 - save location
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@ r1 - FPEXC
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DBGSTR1 "save VFP state %p", r0
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VFPFSTMIA r0, r2 @ save the working registers
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VFPFMRX r2, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present)
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VFPFSTMIA r0 @ save the working registers
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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mov pc, lr
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#endif
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@ -217,8 +217,15 @@ vfp_get_double:
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fmrrd r0, r1, d\dr
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mov pc, lr
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
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mov pc, lr
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.endr
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#endif
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@ virtual register 16 for compare with zero
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@ virtual register 16 (or 32 if VFPv3) for compare with zero
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mov r0, #0
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mov r1, #0
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mov pc, lr
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@ -231,3 +238,10 @@ vfp_put_double:
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fmdrr d\dr, r0, r1
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mov pc, lr
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
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mov pc, lr
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.endr
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#endif
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@ -52,11 +52,11 @@
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#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
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#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12)
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#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
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#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
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#define vfp_get_dm(inst) ((inst & 0x0000000f))
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#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
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#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16)
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#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
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#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
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@ -17,14 +17,18 @@
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/*
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* VFP storage area has:
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* - FPEXC, FPSCR, FPINST and FPINST2.
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* - 16 double precision data registers
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* - an implementation-dependant word of state for FLDMX/FSTMX
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* - 16 or 32 double precision data registers
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* - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
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*
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* FPEXC will always be non-zero once the VFP has been used in this process.
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*/
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struct vfp_hard_struct {
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#ifdef CONFIG_VFPv3
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__u64 fpregs[32];
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#else
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__u64 fpregs[16];
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#endif
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#if __LINUX_ARM_ARCH__ < 6
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__u32 fpmx_state;
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#endif
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@ -35,6 +39,7 @@ struct vfp_hard_struct {
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*/
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__u32 fpinst;
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__u32 fpinst2;
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#ifdef CONFIG_SMP
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__u32 cpu;
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#endif
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@ -7,6 +7,8 @@
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#define FPSID cr0
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#define FPSCR cr1
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#define MVFR1 cr6
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#define MVFR0 cr7
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#define FPEXC cr8
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#define FPINST cr9
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#define FPINST2 cr10
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@ -70,6 +72,10 @@
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#define FPSCR_IXC (1<<4)
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#define FPSCR_IDC (1<<7)
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/* MVFR0 bits */
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#define MVFR0_A_SIMD_BIT (0)
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#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
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/* Bit patterns for decoding the packaged operation descriptors */
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#define VFPOPDESC_LENGTH_BIT (9)
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#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
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@ -15,19 +15,33 @@
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.endm
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@ read all the working registers back into the VFP
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.macro VFPFLDMIA, base
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.macro VFPFLDMIA, base, tmp
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#if __LINUX_ARM_ARCH__ < 6
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LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
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#else
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LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
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#endif
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#ifdef CONFIG_VFPv3
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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.endm
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@ write all the working registers out of the VFP
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.macro VFPFSTMIA, base
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.macro VFPFSTMIA, base, tmp
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#if __LINUX_ARM_ARCH__ < 6
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STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
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#else
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STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
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#endif
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#ifdef CONFIG_VFPv3
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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.endm
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