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riscv: allow case-insensitive ISA string parsing

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According to RISC-V Hart Capabilities Table (RHCT) description in UEFI
Forum ECR, the format of the ISA string is defined in the RISC-V
unprivileged specification which is case-insensitive. However, the
current ISA string parser in the kernel does not support ISA strings
with uppercase letters.

This patch modifies the ISA string parser in the kernel to support
case-insensitive ISA string parsing.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/tencent_B30EED51C7235CA1988890E5C658BE35C107@qq.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Yangyu Chen 2023-05-02 00:17:38 +08:00 • committed by Palmer Dabbelt
parent ac9a78681b
commit 255b34d799
No known key found for this signature in database
GPG key ID: 2E1319F35FBB1889
2 changed files with 19 additions and 19 deletions
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3
arch/riscv/kernel/cpu.c
View file

@ -4,6 +4,7 @@
*/
#include <linux/cpu.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/of.h>
@ -42,7 +43,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
return -ENODEV;
}
if (isa[0] != 'r' || isa[1] != 'v') {
if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') {
pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
return -ENODEV;
}

35
arch/riscv/kernel/cpufeature.c
View file

@ -127,13 +127,10 @@ void __init riscv_fill_hwcap(void)
}
temp = isa;
#if IS_ENABLED(CONFIG_32BIT)
if (!strncmp(isa, "rv32", 4))
if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4))
isa += 4;
#elif IS_ENABLED(CONFIG_64BIT)
if (!strncmp(isa, "rv64", 4))
else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4))
isa += 4;
#endif
/* The riscv,isa DT property must start with rv64 or rv32 */
if (temp == isa)
continue;
@ -157,13 +154,15 @@ void __init riscv_fill_hwcap(void)
break;
}
fallthrough;
case 'S':
case 'x':
case 'X':
case 'z':
case 'Z':
ext_long = true;
/* Multi-letter extension must be delimited */
for (; *isa && *isa != '_'; ++isa)
if (unlikely(!islower(*isa)
&& !isdigit(*isa)))
if (unlikely(!isalnum(*isa)))
ext_err = true;
/* Parse backwards */
ext_end = isa;
@ -174,7 +173,7 @@ void __init riscv_fill_hwcap(void)
/* Skip the minor version */
while (isdigit(*--ext_end))
;
if (ext_end[0] != 'p'
if (tolower(ext_end[0]) != 'p'
|| !isdigit(ext_end[-1])) {
/* Advance it to offset the pre-decrement */
++ext_end;
@ -186,7 +185,7 @@ void __init riscv_fill_hwcap(void)
++ext_end;
break;
default:
if (unlikely(!islower(*ext))) {
if (unlikely(!isalpha(*ext))) {
ext_err = true;
break;
}
@ -196,7 +195,7 @@ void __init riscv_fill_hwcap(void)
/* Skip the minor version */
while (isdigit(*++isa))
;
if (*isa != 'p')
if (tolower(*isa) != 'p')
break;
if (!isdigit(*++isa)) {
--isa;
@ -210,18 +209,18 @@ void __init riscv_fill_hwcap(void)
if (*isa != '_')
--isa;
#define SET_ISA_EXT_MAP(name, bit) \
do { \
if ((ext_end - ext == sizeof(name) - 1) && \
!memcmp(ext, name, sizeof(name) - 1) && \
riscv_isa_extension_check(bit)) \
set_bit(bit, this_isa); \
} while (false) \
#define SET_ISA_EXT_MAP(name, bit) \
do { \
if ((ext_end - ext == sizeof(name) - 1) && \
!strncasecmp(ext, name, sizeof(name) - 1) && \
riscv_isa_extension_check(bit)) \
set_bit(bit, this_isa); \
} while (false) \
if (unlikely(ext_err))
continue;
if (!ext_long) {
int nr = *ext - 'a';
int nr = tolower(*ext) - 'a';
if (riscv_isa_extension_check(nr)) {
this_hwcap |= isa2hwcap[nr];