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drm/radeon: don't reset the MC on IGPs/APUs

Browse source 
The MC isn't part of the GPU per se.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-01-24 15:00:17 -05:00
parent 123bc1832c
commit 24178ec42b
3 changed files with 12 additions and 6 deletions
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6
drivers/gpu/drm/radeon/evergreen.c
View file

@ -2500,8 +2500,10 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
if (reset_mask & RADEON_RESET_VMC)
srbm_soft_reset |= SOFT_RESET_VMC;
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= SOFT_RESET_MC;
if (!(rdev->flags & RADEON_IS_IGP)) {
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= SOFT_RESET_MC;
}
if (grbm_soft_reset) {
tmp = RREG32(GRBM_SOFT_RESET);

6
drivers/gpu/drm/radeon/ni.c
View file

@ -1474,8 +1474,10 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
if (reset_mask & RADEON_RESET_VMC)
srbm_soft_reset |= SOFT_RESET_VMC;
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= SOFT_RESET_MC;
if (!(rdev->flags & RADEON_IS_IGP)) {
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= SOFT_RESET_MC;
}
if (grbm_soft_reset) {
tmp = RREG32(GRBM_SOFT_RESET);

6
drivers/gpu/drm/radeon/r600.c
View file

@ -1475,8 +1475,10 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
if (reset_mask & RADEON_RESET_GRBM)
srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
if (!(rdev->flags & RADEON_IS_IGP)) {
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
}
if (reset_mask & RADEON_RESET_VMC)
srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);