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arm64: sysreg: Add layout for ICH_HCR_EL2
The ICH_HCR_EL2-related macros are missing a number of control bits that we are about to handle. Take this opportunity to fully describe the layout of that register as part of the automatic generation infrastructure. This results in a bit of churn, unfortunately. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250225172930.1850838-2-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Marc Zyngier
Oliver Upton
parent
0ad2507d5d
commit
22513c0d2a
7 changed files with 50 additions and 51 deletions
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@ -562,7 +562,6 @@
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#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
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#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
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#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
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#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
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@ -1003,17 +1002,6 @@
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#define ICH_LR_PRIORITY_SHIFT 48
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#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
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/* ICH_HCR_EL2 bit definitions */
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#define ICH_HCR_EN (1 << 0)
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#define ICH_HCR_UIE (1 << 1)
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#define ICH_HCR_NPIE (1 << 3)
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#define ICH_HCR_TC (1 << 10)
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#define ICH_HCR_TALL0 (1 << 11)
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#define ICH_HCR_TALL1 (1 << 12)
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#define ICH_HCR_TDIR (1 << 14)
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#define ICH_HCR_EOIcount_SHIFT 27
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#define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
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/* ICH_VMCR_EL2 bit definitions */
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#define ICH_VMCR_ACK_CTL_SHIFT 2
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#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
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@ -412,26 +412,26 @@ static const struct trap_bits coarse_trap_bits[] = {
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},
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[CGT_ICH_HCR_TC] = {
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.index = ICH_HCR_EL2,
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.value = ICH_HCR_TC,
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.mask = ICH_HCR_TC,
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.value = ICH_HCR_EL2_TC,
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.mask = ICH_HCR_EL2_TC,
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.behaviour = BEHAVE_FORWARD_RW,
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},
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[CGT_ICH_HCR_TALL0] = {
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.index = ICH_HCR_EL2,
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.value = ICH_HCR_TALL0,
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.mask = ICH_HCR_TALL0,
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.value = ICH_HCR_EL2_TALL0,
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.mask = ICH_HCR_EL2_TALL0,
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.behaviour = BEHAVE_FORWARD_RW,
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},
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[CGT_ICH_HCR_TALL1] = {
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.index = ICH_HCR_EL2,
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.value = ICH_HCR_TALL1,
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.mask = ICH_HCR_TALL1,
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.value = ICH_HCR_EL2_TALL1,
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.mask = ICH_HCR_EL2_TALL1,
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.behaviour = BEHAVE_FORWARD_RW,
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},
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[CGT_ICH_HCR_TDIR] = {
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.index = ICH_HCR_EL2,
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.value = ICH_HCR_TDIR,
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.mask = ICH_HCR_TDIR,
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.value = ICH_HCR_EL2_TDIR,
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.mask = ICH_HCR_EL2_TDIR,
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.behaviour = BEHAVE_FORWARD_RW,
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},
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};
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@ -218,7 +218,7 @@ void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if)
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elrsr = read_gicreg(ICH_ELRSR_EL2);
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write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2);
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write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EL2_En, ICH_HCR_EL2);
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for (i = 0; i < used_lrs; i++) {
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if (elrsr & (1 << i))
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@ -274,7 +274,7 @@ void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if)
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* system registers to trap to EL1 (duh), force ICC_SRE_EL1.SRE to 1
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* so that the trap bits can take effect. Yes, we *loves* the GIC.
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*/
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if (!(cpu_if->vgic_hcr & ICH_HCR_EN)) {
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if (!(cpu_if->vgic_hcr & ICH_HCR_EL2_En)) {
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write_gicreg(ICC_SRE_EL1_SRE, ICC_SRE_EL1);
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isb();
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} else if (!cpu_if->vgic_sre) {
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@ -752,7 +752,7 @@ static void __vgic_v3_bump_eoicount(void)
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u32 hcr;
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hcr = read_gicreg(ICH_HCR_EL2);
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hcr += 1 << ICH_HCR_EOIcount_SHIFT;
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hcr += 1 << ICH_HCR_EL2_EOIcount_SHIFT;
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write_gicreg(hcr, ICH_HCR_EL2);
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}
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@ -1069,7 +1069,7 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu,
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case SYS_ICC_EOIR0_EL1:
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case SYS_ICC_HPPIR0_EL1:
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case SYS_ICC_IAR0_EL1:
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return ich_hcr & ICH_HCR_TALL0;
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return ich_hcr & ICH_HCR_EL2_TALL0;
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case SYS_ICC_IGRPEN1_EL1:
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if (is_read &&
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@ -1090,10 +1090,10 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu,
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case SYS_ICC_EOIR1_EL1:
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case SYS_ICC_HPPIR1_EL1:
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case SYS_ICC_IAR1_EL1:
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return ich_hcr & ICH_HCR_TALL1;
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return ich_hcr & ICH_HCR_EL2_TALL1;
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case SYS_ICC_DIR_EL1:
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if (ich_hcr & ICH_HCR_TDIR)
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if (ich_hcr & ICH_HCR_EL2_TDIR)
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return true;
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fallthrough;
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@ -1101,7 +1101,7 @@ static bool __vgic_v3_check_trap_forwarding(struct kvm_vcpu *vcpu,
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case SYS_ICC_RPR_EL1:
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case SYS_ICC_CTLR_EL1:
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case SYS_ICC_PMR_EL1:
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return ich_hcr & ICH_HCR_TC;
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return ich_hcr & ICH_HCR_EL2_TC;
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default:
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return false;
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@ -24,7 +24,7 @@ void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
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cpuif->vgic_hcr |= ICH_HCR_UIE;
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cpuif->vgic_hcr |= ICH_HCR_EL2_UIE;
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}
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static bool lr_signals_eoi_mi(u64 lr_val)
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@ -42,7 +42,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
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DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
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cpuif->vgic_hcr &= ~ICH_HCR_UIE;
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cpuif->vgic_hcr &= ~ICH_HCR_EL2_UIE;
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for (lr = 0; lr < cpuif->used_lrs; lr++) {
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u64 val = cpuif->vgic_lr[lr];
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@ -292,7 +292,7 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
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ICH_VTR_PRI_BITS_SHIFT) + 1;
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/* Get the show on the road... */
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vgic_v3->vgic_hcr = ICH_HCR_EN;
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vgic_v3->vgic_hcr = ICH_HCR_EL2_En;
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}
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void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
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@ -301,18 +301,19 @@ void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
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/* Hide GICv3 sysreg if necessary */
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if (!kvm_has_gicv3(vcpu->kvm)) {
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vgic_v3->vgic_hcr |= ICH_HCR_TALL0 | ICH_HCR_TALL1 | ICH_HCR_TC;
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vgic_v3->vgic_hcr |= (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 |
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ICH_HCR_EL2_TC);
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return;
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}
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if (group0_trap)
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vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
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vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL0;
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if (group1_trap)
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vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
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vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL1;
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if (common_trap)
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vgic_v3->vgic_hcr |= ICH_HCR_TC;
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vgic_v3->vgic_hcr |= ICH_HCR_EL2_TC;
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if (dir_trap)
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vgic_v3->vgic_hcr |= ICH_HCR_TDIR;
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vgic_v3->vgic_hcr |= ICH_HCR_EL2_TDIR;
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}
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int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
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@ -3035,6 +3035,28 @@ Field 31:16 PhyPARTID29
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Field 15:0 PhyPARTID28
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EndSysreg
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Sysreg ICH_HCR_EL2 3 4 12 11 0
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Res0 63:32
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Field 31:27 EOIcount
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Res0 26:16
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Field 15 DVIM
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Field 14 TDIR
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Field 13 TSEI
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Field 12 TALL1
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Field 11 TALL0
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Field 10 TC
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Res0 9
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Field 8 vSGIEOICount
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Field 7 VGrp1DIE
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Field 6 VGrp1EIE
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Field 5 VGrp0DIE
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Field 4 VGrp0EIE
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Field 3 NPIE
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Field 2 LRENPIE
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Field 1 UIE
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Field 0 En
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EndSysreg
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Sysreg CONTEXTIDR_EL2 3 4 13 0 1
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Fields CONTEXTIDR_ELx
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EndSysreg
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@ -409,15 +409,15 @@ static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)
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* in use, and be cleared when coming back from the handler.
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*/
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if (is_kernel_in_hyp_mode() &&
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(read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&
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(read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) &&
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read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {
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generic_handle_domain_irq(aic_irqc->hw_domain,
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AIC_FIQ_HWIRQ(AIC_VGIC_MI));
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if (unlikely((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&
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if (unlikely((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_En) &&
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read_sysreg_s(SYS_ICH_MISR_EL2))) {
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pr_err_ratelimited("vGIC IRQ fired and not handled by KVM, disabling.\n");
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sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);
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sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0);
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}
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}
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}
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@ -841,7 +841,7 @@ static int aic_init_cpu(unsigned int cpu)
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VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);
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/* vGIC maintenance IRQ */
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sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);
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sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EL2_En, 0);
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}
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/* PMC FIQ */
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@ -558,7 +558,6 @@
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#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
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#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
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#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
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#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
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@ -999,17 +998,6 @@
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#define ICH_LR_PRIORITY_SHIFT 48
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#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
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/* ICH_HCR_EL2 bit definitions */
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#define ICH_HCR_EN (1 << 0)
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#define ICH_HCR_UIE (1 << 1)
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#define ICH_HCR_NPIE (1 << 3)
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#define ICH_HCR_TC (1 << 10)
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#define ICH_HCR_TALL0 (1 << 11)
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#define ICH_HCR_TALL1 (1 << 12)
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#define ICH_HCR_TDIR (1 << 14)
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#define ICH_HCR_EOIcount_SHIFT 27
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#define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
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/* ICH_VMCR_EL2 bit definitions */
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#define ICH_VMCR_ACK_CTL_SHIFT 2
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#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
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