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arm64: dts: apple: t8015: Add CPU caches

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Add information about CPU caches in Apple A11 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-9-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Nick Chan 2025-02-20 20:21:50 +08:00 • committed by Sven Peter
parent 0b311f8d69
commit 21da4ec75a
1 changed files with 32 additions and 0 deletions
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32
arch/arm64/boot/dts/apple/t8015.dtsi
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@ -63,6 +63,9 @@
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_e1: cpu@1 {
@ -74,6 +77,9 @@
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_e2: cpu@2 {
@ -85,6 +91,9 @@
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_e3: cpu@3 {
@ -96,6 +105,9 @@
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_0>;
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
};
cpu_p0: cpu@10004 {
@ -107,6 +119,9 @@
capacity-dmips-mhz = <1024>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu_p1: cpu@10005 {
@ -118,6 +133,23 @@
capacity-dmips-mhz = <1024>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache_1>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
};
l2_cache_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x800000>;
};
};