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pwm: sophgo-sg2042: Add support for SG2044
Add PWM controller for SG2044 on base of SG2042. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Longbin Li <looong.bin@gmail.com> Link: https://lore.kernel.org/r/20250528101139.28702-4-looong.bin@gmail.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
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1 changed files with 87 additions and 2 deletions
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@ -13,6 +13,7 @@
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* the running period.
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* - When PERIOD and HLPERIOD is set to 0, the PWM wave output will
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* be stopped and the output is pulled to high.
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* - SG2044 supports both polarities, SG2042 only normal polarity.
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* See the datasheet [1] for more details.
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* [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM
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*/
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@ -41,6 +42,10 @@
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#define SG2042_PWM_HLPERIOD(chan) ((chan) * 8 + 0)
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#define SG2042_PWM_PERIOD(chan) ((chan) * 8 + 4)
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#define SG2044_PWM_POLARITY 0x40
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#define SG2044_PWM_PWMSTART 0x44
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#define SG2044_PWM_OE 0xd0
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#define SG2042_PWM_CHANNELNUM 4
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/**
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@ -84,8 +89,8 @@ static void pwm_sg2042_set_dutycycle(struct pwm_chip *chip, struct pwm_device *p
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period_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSEC_PER_SEC), U32_MAX);
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hlperiod_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->duty_cycle, NSEC_PER_SEC), U32_MAX);
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dev_dbg(pwmchip_parent(chip), "chan[%u]: PERIOD=%u, HLPERIOD=%u\n",
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pwm->hwpwm, period_ticks, hlperiod_ticks);
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dev_dbg(pwmchip_parent(chip), "chan[%u]: ENABLE=%u, PERIOD=%u, HLPERIOD=%u, POLARITY=%u\n",
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pwm->hwpwm, state->enabled, period_ticks, hlperiod_ticks, state->polarity);
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pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks);
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}
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@ -135,6 +140,74 @@ static int pwm_sg2042_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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return 0;
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}
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static void pwm_sg2044_set_outputen(struct sg2042_pwm_ddata *ddata, struct pwm_device *pwm,
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bool enabled)
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{
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u32 pwmstart;
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pwmstart = readl(ddata->base + SG2044_PWM_PWMSTART);
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if (enabled)
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pwmstart |= BIT(pwm->hwpwm);
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else
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pwmstart &= ~BIT(pwm->hwpwm);
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writel(pwmstart, ddata->base + SG2044_PWM_PWMSTART);
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}
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static void pwm_sg2044_set_outputdir(struct sg2042_pwm_ddata *ddata, struct pwm_device *pwm,
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bool enabled)
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{
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u32 pwm_oe;
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pwm_oe = readl(ddata->base + SG2044_PWM_OE);
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if (enabled)
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pwm_oe |= BIT(pwm->hwpwm);
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else
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pwm_oe &= ~BIT(pwm->hwpwm);
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writel(pwm_oe, ddata->base + SG2044_PWM_OE);
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}
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static void pwm_sg2044_set_polarity(struct sg2042_pwm_ddata *ddata, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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u32 pwm_polarity;
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pwm_polarity = readl(ddata->base + SG2044_PWM_POLARITY);
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if (state->polarity == PWM_POLARITY_NORMAL)
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pwm_polarity &= ~BIT(pwm->hwpwm);
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else
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pwm_polarity |= BIT(pwm->hwpwm);
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writel(pwm_polarity, ddata->base + SG2044_PWM_POLARITY);
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}
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static int pwm_sg2044_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
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pwm_sg2044_set_polarity(ddata, pwm, state);
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pwm_sg2042_set_dutycycle(chip, pwm, state);
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/*
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* re-enable PWMSTART to refresh the register period
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*/
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pwm_sg2044_set_outputen(ddata, pwm, false);
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if (!state->enabled)
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return 0;
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pwm_sg2044_set_outputdir(ddata, pwm, true);
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pwm_sg2044_set_outputen(ddata, pwm, true);
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return 0;
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}
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static const struct sg2042_chip_data sg2042_chip_data = {
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.ops = {
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.apply = pwm_sg2042_apply,
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@ -142,11 +215,22 @@ static const struct sg2042_chip_data sg2042_chip_data = {
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},
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};
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static const struct sg2042_chip_data sg2044_chip_data = {
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.ops = {
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.apply = pwm_sg2044_apply,
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.get_state = pwm_sg2042_get_state,
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},
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};
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static const struct of_device_id sg2042_pwm_ids[] = {
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{
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.compatible = "sophgo,sg2042-pwm",
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.data = &sg2042_chip_data
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},
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{
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.compatible = "sophgo,sg2044-pwm",
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.data = &sg2044_chip_data
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, sg2042_pwm_ids);
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@ -212,5 +296,6 @@ static struct platform_driver pwm_sg2042_driver = {
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module_platform_driver(pwm_sg2042_driver);
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MODULE_AUTHOR("Chen Wang");
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MODULE_AUTHOR("Longbin Li <looong.bin@gmail.com>");
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MODULE_DESCRIPTION("Sophgo SG2042 PWM driver");
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MODULE_LICENSE("GPL");
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