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dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

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Add PLL clock inputs from PLL clock generator.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu 2023-07-17 10:30:36 +08:00 • committed by Conor Dooley
parent c81f7845b2
commit 2110add84b
1 changed files with 16 additions and 2 deletions
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18
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
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@ -27,6 +27,9 @@ properties:
- description: External I2S RX left/right channel clock
- description: External TDM clock
- description: External audio master clock
- description: PLL0
- description: PLL1
- description: PLL2
- items:
- description: Main Oscillator (24 MHz)
@ -38,6 +41,9 @@ properties:
- description: External I2S RX left/right channel clock
- description: External TDM clock
- description: External audio master clock
- description: PLL0
- description: PLL1
- description: PLL2
clock-names:
oneOf:
@ -52,6 +58,9 @@ properties:
- const: i2srx_lrck_ext
- const: tdm_ext
- const: mclk_ext
- const: pll0_out
- const: pll1_out
- const: pll2_out
- items:
- const: osc
@ -63,6 +72,9 @@ properties:
- const: i2srx_lrck_ext
- const: tdm_ext
- const: mclk_ext
- const: pll0_out
- const: pll1_out
- const: pll2_out
'#clock-cells':
const: 1
@ -93,12 +105,14 @@ examples:
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>;
<&tdm_ext>, <&mclk_ext>,
<&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext";
"tdm_ext", "mclk_ext",
"pll0_out", "pll1_out", "pll2_out";
#clock-cells = <1>;
#reset-cells = <1>;
};