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net: airoha: Add sched ETS offload support
Introduce support for ETS Qdisc offload available on the Airoha EN7581 ethernet controller. In order to be effective, ETS Qdisc must configured as leaf of a HTB Qdisc (HTB Qdisc offload will be added in the following patch). ETS Qdisc available on EN7581 ethernet controller supports at most 8 concurrent bands (QoS queues). We can enable an ETS Qdisc for each available QoS channel. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Lorenzo Bianconi
Paolo Abeni
parent
2b288b8156
commit
20bf7d07c9
1 changed files with 195 additions and 1 deletions
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@ -15,6 +15,7 @@
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#include <linux/u64_stats_sync.h>
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#include <net/dsa.h>
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#include <net/page_pool/helpers.h>
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#include <net/pkt_cls.h>
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#include <uapi/linux/ppp_defs.h>
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#define AIROHA_MAX_NUM_GDM_PORTS 1
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@ -543,9 +544,24 @@
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#define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
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#define INGRESS_FAST_TICK_MASK GENMASK(15, 0)
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#define REG_QUEUE_CLOSE_CFG(_n) (0x00a0 + ((_n) & 0xfc))
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#define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3))
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#define REG_TXQ_DIS_CFG_BASE(_n) ((_n) ? 0x20a0 : 0x00a0)
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#define REG_TXQ_DIS_CFG(_n, _m) (REG_TXQ_DIS_CFG_BASE((_n)) + (_m) << 2)
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#define REG_CNTR_CFG(_n) (0x0400 + ((_n) << 3))
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#define CNTR_EN_MASK BIT(31)
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#define CNTR_ALL_CHAN_EN_MASK BIT(30)
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#define CNTR_ALL_QUEUE_EN_MASK BIT(29)
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#define CNTR_ALL_DSCP_RING_EN_MASK BIT(28)
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#define CNTR_SRC_MASK GENMASK(27, 24)
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#define CNTR_DSCP_RING_MASK GENMASK(20, 16)
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#define CNTR_CHAN_MASK GENMASK(7, 3)
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#define CNTR_QUEUE_MASK GENMASK(2, 0)
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#define REG_CNTR_VAL(_n) (0x0404 + ((_n) << 3))
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#define REG_LMGR_INIT_CFG 0x1000
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#define LMGR_INIT_START BIT(31)
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#define LMGR_SRAM_MODE_MASK BIT(30)
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@ -571,9 +587,19 @@
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#define TWRR_WEIGHT_SCALE_MASK BIT(31)
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#define TWRR_WEIGHT_BASE_MASK BIT(3)
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#define REG_TXWRR_WEIGHT_CFG 0x1024
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#define TWRR_RW_CMD_MASK BIT(31)
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#define TWRR_RW_CMD_DONE BIT(30)
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#define TWRR_CHAN_IDX_MASK GENMASK(23, 19)
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#define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)
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#define TWRR_VALUE_MASK GENMASK(15, 0)
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#define REG_PSE_BUF_USAGE_CFG 0x1028
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#define PSE_BUF_ESTIMATE_EN_MASK BIT(29)
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#define REG_CHAN_QOS_MODE(_n) (0x1040 + ((_n) << 2))
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#define CHAN_QOS_MODE_MASK(_n) GENMASK(2 + ((_n) << 2), (_n) << 2)
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#define REG_GLB_TRTCM_CFG 0x1080
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#define GLB_TRTCM_EN_MASK BIT(31)
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#define GLB_TRTCM_MODE_MASK BIT(30)
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@ -722,6 +748,17 @@ enum {
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FE_PSE_PORT_DROP = 0xf,
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};
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enum tx_sched_mode {
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TC_SCH_WRR8,
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TC_SCH_SP,
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TC_SCH_WRR7,
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TC_SCH_WRR6,
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TC_SCH_WRR5,
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TC_SCH_WRR4,
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TC_SCH_WRR3,
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TC_SCH_WRR2,
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};
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struct airoha_queue_entry {
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union {
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void *buf;
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@ -812,6 +849,10 @@ struct airoha_gdm_port {
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int id;
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struct airoha_hw_stats stats;
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/* qos stats counters */
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u64 cpu_tx_packets;
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u64 fwd_tx_packets;
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};
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struct airoha_eth {
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@ -1961,6 +2002,27 @@ static void airoha_qdma_init_qos(struct airoha_qdma *qdma)
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FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40));
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}
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static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)
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{
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int i;
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for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) {
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/* Tx-cpu transferred count */
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airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0);
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airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
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CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
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CNTR_ALL_DSCP_RING_EN_MASK |
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FIELD_PREP(CNTR_CHAN_MASK, i));
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/* Tx-fwd transferred count */
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airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0);
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airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
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CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
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CNTR_ALL_DSCP_RING_EN_MASK |
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FIELD_PREP(CNTR_SRC_MASK, 1) |
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FIELD_PREP(CNTR_CHAN_MASK, i));
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}
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}
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static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
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{
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int i;
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@ -2011,6 +2073,7 @@ static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
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airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG,
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TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN);
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airoha_qdma_init_qos_stats(qdma);
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return 0;
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}
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@ -2638,6 +2701,135 @@ airoha_ethtool_get_rmon_stats(struct net_device *dev,
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} while (u64_stats_fetch_retry(&port->stats.syncp, start));
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}
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static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port,
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int channel, enum tx_sched_mode mode,
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const u16 *weights, u8 n_weights)
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{
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int i;
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for (i = 0; i < AIROHA_NUM_TX_RING; i++)
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airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
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TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i));
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for (i = 0; i < n_weights; i++) {
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u32 status;
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int err;
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airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG,
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TWRR_RW_CMD_MASK |
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FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) |
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FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) |
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FIELD_PREP(TWRR_VALUE_MASK, weights[i]));
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err = read_poll_timeout(airoha_qdma_rr, status,
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status & TWRR_RW_CMD_DONE,
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USEC_PER_MSEC, 10 * USEC_PER_MSEC,
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true, port->qdma,
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REG_TXWRR_WEIGHT_CFG);
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if (err)
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return err;
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}
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airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3),
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CHAN_QOS_MODE_MASK(channel),
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mode << __ffs(CHAN_QOS_MODE_MASK(channel)));
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return 0;
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}
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static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port,
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int channel)
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{
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static const u16 w[AIROHA_NUM_QOS_QUEUES] = {};
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return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w,
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ARRAY_SIZE(w));
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}
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static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port,
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int channel,
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struct tc_ets_qopt_offload *opt)
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{
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struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params;
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enum tx_sched_mode mode = TC_SCH_SP;
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u16 w[AIROHA_NUM_QOS_QUEUES] = {};
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int i, nstrict = 0;
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if (p->bands > AIROHA_NUM_QOS_QUEUES)
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return -EINVAL;
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for (i = 0; i < p->bands; i++) {
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if (!p->quanta[i])
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nstrict++;
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}
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/* this configuration is not supported by the hw */
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if (nstrict == AIROHA_NUM_QOS_QUEUES - 1)
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return -EINVAL;
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for (i = 0; i < p->bands - nstrict; i++)
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w[i] = p->weights[nstrict + i];
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if (!nstrict)
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mode = TC_SCH_WRR8;
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else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1)
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mode = nstrict + 1;
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return airoha_qdma_set_chan_tx_sched(port, channel, mode, w,
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ARRAY_SIZE(w));
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}
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static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port,
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int channel,
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struct tc_ets_qopt_offload *opt)
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{
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u64 cpu_tx_packets = airoha_qdma_rr(port->qdma,
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REG_CNTR_VAL(channel << 1));
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u64 fwd_tx_packets = airoha_qdma_rr(port->qdma,
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REG_CNTR_VAL((channel << 1) + 1));
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u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) +
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(fwd_tx_packets - port->fwd_tx_packets);
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_bstats_update(opt->stats.bstats, 0, tx_packets);
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port->cpu_tx_packets = cpu_tx_packets;
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port->fwd_tx_packets = fwd_tx_packets;
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return 0;
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}
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static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port,
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struct tc_ets_qopt_offload *opt)
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{
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int channel = TC_H_MAJ(opt->handle) >> 16;
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if (opt->parent == TC_H_ROOT)
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return -EINVAL;
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switch (opt->command) {
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case TC_ETS_REPLACE:
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return airoha_qdma_set_tx_ets_sched(port, channel, opt);
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case TC_ETS_DESTROY:
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/* PRIO is default qdisc scheduler */
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return airoha_qdma_set_tx_prio_sched(port, channel);
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case TC_ETS_STATS:
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return airoha_qdma_get_tx_ets_stats(port, channel, opt);
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default:
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return -EOPNOTSUPP;
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}
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}
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static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type,
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void *type_data)
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{
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struct airoha_gdm_port *port = netdev_priv(dev);
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switch (type) {
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case TC_SETUP_QDISC_ETS:
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return airoha_tc_setup_qdisc_ets(port, type_data);
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default:
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return -EOPNOTSUPP;
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}
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}
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static const struct net_device_ops airoha_netdev_ops = {
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.ndo_init = airoha_dev_init,
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.ndo_open = airoha_dev_open,
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@ -2646,6 +2838,7 @@ static const struct net_device_ops airoha_netdev_ops = {
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.ndo_start_xmit = airoha_dev_xmit,
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.ndo_get_stats64 = airoha_dev_get_stats64,
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.ndo_set_mac_address = airoha_dev_set_macaddr,
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.ndo_setup_tc = airoha_dev_tc_setup,
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};
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static const struct ethtool_ops airoha_ethtool_ops = {
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@ -2695,7 +2888,8 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth, struct device_node *np)
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dev->watchdog_timeo = 5 * HZ;
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dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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NETIF_F_TSO6 | NETIF_F_IPV6_CSUM |
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NETIF_F_SG | NETIF_F_TSO;
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NETIF_F_SG | NETIF_F_TSO |
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NETIF_F_HW_TC;
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dev->features |= dev->hw_features;
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dev->dev.of_node = np;
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dev->irq = qdma->irq;
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