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drm/amdgpu/mes: extend mes framework to support multiple mes pipes
Add support for multiple mes pipes, so that reuse the existing code to initialize more mes pipe and queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao
Alex Deucher
parent
b608e785e1
commit
207e8bbe66
2 changed files with 149 additions and 101 deletions
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@ -47,6 +47,12 @@ enum amdgpu_mes_priority_level {
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struct amdgpu_mes_funcs;
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enum admgpu_mes_pipe {
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AMDGPU_MES_SCHED_PIPE = 0,
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AMDGPU_MES_KIQ_PIPE,
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AMDGPU_MAX_MES_PIPES = 2,
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};
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struct amdgpu_mes {
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struct amdgpu_device *adev;
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@ -68,27 +74,28 @@ struct amdgpu_mes {
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struct amdgpu_ring ring;
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const struct firmware *fw;
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const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
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/* mes ucode */
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struct amdgpu_bo *ucode_fw_obj;
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uint64_t ucode_fw_gpu_addr;
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uint32_t *ucode_fw_ptr;
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uint32_t ucode_fw_version;
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uint64_t uc_start_addr;
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struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
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uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
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uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES];
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uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
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/* mes ucode data */
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struct amdgpu_bo *data_fw_obj;
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uint64_t data_fw_gpu_addr;
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uint32_t *data_fw_ptr;
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uint32_t data_fw_version;
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uint64_t data_start_addr;
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struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
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uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
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uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES];
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uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
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/* eop gpu obj */
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struct amdgpu_bo *eop_gpu_obj;
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uint64_t eop_gpu_addr;
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struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
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void *mqd_backup;
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void *mqd_backup[AMDGPU_MAX_MES_PIPES];
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struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
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uint32_t vmid_mask_gfxhub;
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uint32_t vmid_mask_mmhub;
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@ -269,7 +269,8 @@ static const struct amdgpu_mes_funcs mes_v10_1_funcs = {
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.resume_gang = mes_v10_1_resume_gang,
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};
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static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
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static int mes_v10_1_init_microcode(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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const char *chip_name;
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char fw_name[30];
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@ -288,40 +289,56 @@ static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
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BUG();
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}
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", chip_name);
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err = request_firmware(&adev->mes.fw, fw_name, adev->dev);
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if (pipe == AMDGPU_MES_SCHED_PIPE)
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
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chip_name);
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else
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BUG();
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err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
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if (err)
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return err;
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err = amdgpu_ucode_validate(adev->mes.fw);
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err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
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if (err) {
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release_firmware(adev->mes.fw);
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adev->mes.fw = NULL;
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release_firmware(adev->mes.fw[pipe]);
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adev->mes.fw[pipe] = NULL;
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return err;
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}
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mes_hdr = (const struct mes_firmware_header_v1_0 *)adev->mes.fw->data;
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adev->mes.ucode_fw_version = le32_to_cpu(mes_hdr->mes_ucode_version);
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adev->mes.ucode_fw_version =
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mes_hdr = (const struct mes_firmware_header_v1_0 *)
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adev->mes.fw[pipe]->data;
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adev->mes.ucode_fw_version[pipe] =
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le32_to_cpu(mes_hdr->mes_ucode_version);
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adev->mes.ucode_fw_version[pipe] =
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le32_to_cpu(mes_hdr->mes_ucode_data_version);
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adev->mes.uc_start_addr =
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adev->mes.uc_start_addr[pipe] =
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le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
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((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
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adev->mes.data_start_addr =
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adev->mes.data_start_addr[pipe] =
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le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
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((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MES];
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info->ucode_id = AMDGPU_UCODE_ID_CP_MES;
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info->fw = adev->mes.fw;
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int ucode, ucode_data;
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if (pipe == AMDGPU_MES_SCHED_PIPE) {
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ucode = AMDGPU_UCODE_ID_CP_MES;
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ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
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} else {
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BUG();
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}
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info = &adev->firmware.ucode[ucode];
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info->ucode_id = ucode;
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info->fw = adev->mes.fw[pipe];
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
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PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MES_DATA];
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info->ucode_id = AMDGPU_UCODE_ID_CP_MES_DATA;
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info->fw = adev->mes.fw;
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info = &adev->firmware.ucode[ucode_data];
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info->ucode_id = ucode_data;
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info->fw = adev->mes.fw[pipe];
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
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PAGE_SIZE);
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@ -330,13 +347,15 @@ static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
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return 0;
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}
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static void mes_v10_1_free_microcode(struct amdgpu_device *adev)
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static void mes_v10_1_free_microcode(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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release_firmware(adev->mes.fw);
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adev->mes.fw = NULL;
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release_firmware(adev->mes.fw[pipe]);
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adev->mes.fw[pipe] = NULL;
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}
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static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev)
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static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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int r;
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const struct mes_firmware_header_v1_0 *mes_hdr;
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@ -344,31 +363,32 @@ static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev)
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unsigned fw_size;
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mes_hdr = (const struct mes_firmware_header_v1_0 *)
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adev->mes.fw->data;
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adev->mes.fw[pipe]->data;
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fw_data = (const __le32 *)(adev->mes.fw->data +
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fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
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le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
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fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
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r = amdgpu_bo_create_reserved(adev, fw_size,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.ucode_fw_obj,
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&adev->mes.ucode_fw_gpu_addr,
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(void **)&adev->mes.ucode_fw_ptr);
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&adev->mes.ucode_fw_obj[pipe],
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&adev->mes.ucode_fw_gpu_addr[pipe],
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(void **)&adev->mes.ucode_fw_ptr[pipe]);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
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return r;
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}
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memcpy(adev->mes.ucode_fw_ptr, fw_data, fw_size);
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memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
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amdgpu_bo_kunmap(adev->mes.ucode_fw_obj);
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amdgpu_bo_unreserve(adev->mes.ucode_fw_obj);
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amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
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amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
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return 0;
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}
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static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev)
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static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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int r;
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const struct mes_firmware_header_v1_0 *mes_hdr;
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@ -376,53 +396,63 @@ static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev)
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unsigned fw_size;
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mes_hdr = (const struct mes_firmware_header_v1_0 *)
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adev->mes.fw->data;
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adev->mes.fw[pipe]->data;
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fw_data = (const __le32 *)(adev->mes.fw->data +
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fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
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le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
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fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
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r = amdgpu_bo_create_reserved(adev, fw_size,
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64 * 1024, AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.data_fw_obj,
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&adev->mes.data_fw_gpu_addr,
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(void **)&adev->mes.data_fw_ptr);
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&adev->mes.data_fw_obj[pipe],
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&adev->mes.data_fw_gpu_addr[pipe],
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(void **)&adev->mes.data_fw_ptr[pipe]);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
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return r;
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}
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memcpy(adev->mes.data_fw_ptr, fw_data, fw_size);
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memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
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amdgpu_bo_kunmap(adev->mes.data_fw_obj);
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amdgpu_bo_unreserve(adev->mes.data_fw_obj);
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amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
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amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
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return 0;
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}
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static void mes_v10_1_free_ucode_buffers(struct amdgpu_device *adev)
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static void mes_v10_1_free_ucode_buffers(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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amdgpu_bo_free_kernel(&adev->mes.data_fw_obj,
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&adev->mes.data_fw_gpu_addr,
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(void **)&adev->mes.data_fw_ptr);
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amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
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&adev->mes.data_fw_gpu_addr[pipe],
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(void **)&adev->mes.data_fw_ptr[pipe]);
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amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj,
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&adev->mes.ucode_fw_gpu_addr,
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(void **)&adev->mes.ucode_fw_ptr);
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amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
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&adev->mes.ucode_fw_gpu_addr[pipe],
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(void **)&adev->mes.ucode_fw_ptr[pipe]);
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}
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static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable)
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{
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uint32_t data = 0;
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uint32_t pipe, data = 0;
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if (enable) {
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data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);
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data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
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WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
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/* set ucode start address */
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WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
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(uint32_t)(adev->mes.uc_start_addr) >> 2);
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mutex_lock(&adev->srbm_mutex);
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for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
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if (!adev->enable_mes_kiq &&
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pipe == AMDGPU_MES_KIQ_PIPE)
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continue;
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nv_grbm_select(adev, 3, pipe, 0, 0);
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WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
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(uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2);
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}
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nv_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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/* clear BYPASS_UNCACHED to avoid hangs after interrupt. */
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data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL);
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@ -445,50 +475,51 @@ static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable)
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}
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/* This function is for backdoor MES firmware */
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static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
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static int mes_v10_1_load_microcode(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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int r;
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uint32_t data;
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if (!adev->mes.fw)
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mes_v10_1_enable(adev, false);
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if (!adev->mes.fw[pipe])
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return -EINVAL;
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r = mes_v10_1_allocate_ucode_buffer(adev);
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r = mes_v10_1_allocate_ucode_buffer(adev, pipe);
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if (r)
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return r;
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r = mes_v10_1_allocate_ucode_data_buffer(adev);
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r = mes_v10_1_allocate_ucode_data_buffer(adev, pipe);
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if (r) {
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mes_v10_1_free_ucode_buffers(adev);
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mes_v10_1_free_ucode_buffers(adev, pipe);
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return r;
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}
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mes_v10_1_enable(adev, false);
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WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0);
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mutex_lock(&adev->srbm_mutex);
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/* me=3, pipe=0, queue=0 */
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nv_grbm_select(adev, 3, 0, 0, 0);
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nv_grbm_select(adev, 3, pipe, 0, 0);
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/* set ucode start address */
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WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
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(uint32_t)(adev->mes.uc_start_addr) >> 2);
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(uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2);
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/* set ucode fimrware address */
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WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO,
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lower_32_bits(adev->mes.ucode_fw_gpu_addr));
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lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
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WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI,
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upper_32_bits(adev->mes.ucode_fw_gpu_addr));
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upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
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/* set ucode instruction cache boundary to 2M-1 */
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WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF);
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/* set ucode data firmware address */
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WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO,
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lower_32_bits(adev->mes.data_fw_gpu_addr));
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lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
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WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI,
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upper_32_bits(adev->mes.data_fw_gpu_addr));
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upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
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/* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
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WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);
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@ -538,25 +569,26 @@ static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
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return 0;
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}
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static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev)
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static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev,
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enum admgpu_mes_pipe pipe)
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{
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int r;
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u32 *eop;
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r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.eop_gpu_obj,
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&adev->mes.eop_gpu_addr,
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(void **)&eop);
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.eop_gpu_obj[pipe],
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&adev->mes.eop_gpu_addr[pipe],
|
||||
(void **)&eop);
|
||||
if (r) {
|
||||
dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
memset(eop, 0, adev->mes.eop_gpu_obj->tbo.base.size);
|
||||
memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
|
||||
|
||||
amdgpu_bo_kunmap(adev->mes.eop_gpu_obj);
|
||||
amdgpu_bo_unreserve(adev->mes.eop_gpu_obj);
|
||||
amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
|
||||
amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -727,7 +759,7 @@ static void mes_v10_1_queue_init_register(struct amdgpu_ring *ring)
|
|||
uint32_t data = 0;
|
||||
|
||||
mutex_lock(&adev->srbm_mutex);
|
||||
nv_grbm_select(adev, 3, 0, 0, 0);
|
||||
nv_grbm_select(adev, 3, ring->pipe, 0, 0);
|
||||
|
||||
/* set CP_HQD_VMID.VMID = 0. */
|
||||
data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID);
|
||||
|
|
@ -842,8 +874,8 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
|
|||
|
||||
ring->ring_obj = NULL;
|
||||
ring->use_doorbell = true;
|
||||
ring->doorbell_index = adev->doorbell_index.mes_ring << 1;
|
||||
ring->eop_gpu_addr = adev->mes.eop_gpu_addr;
|
||||
ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
|
||||
ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
|
||||
ring->no_scheduler = true;
|
||||
sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
|
||||
|
||||
|
|
@ -851,10 +883,16 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
|
|||
AMDGPU_RING_PRIO_DEFAULT, NULL);
|
||||
}
|
||||
|
||||
static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
|
||||
static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev,
|
||||
enum admgpu_mes_pipe pipe)
|
||||
{
|
||||
int r, mqd_size = sizeof(struct v10_compute_mqd);
|
||||
struct amdgpu_ring *ring = &adev->mes.ring;
|
||||
struct amdgpu_ring *ring;
|
||||
|
||||
if (pipe == AMDGPU_MES_SCHED_PIPE)
|
||||
ring = &adev->mes.ring;
|
||||
else
|
||||
BUG();
|
||||
|
||||
if (ring->mqd_obj)
|
||||
return 0;
|
||||
|
|
@ -868,8 +906,8 @@ static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
|
|||
}
|
||||
|
||||
/* prepare MQD backup */
|
||||
adev->mes.mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
|
||||
if (!adev->mes.mqd_backup)
|
||||
adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
|
||||
if (!adev->mes.mqd_backup[pipe])
|
||||
dev_warn(adev->dev,
|
||||
"no memory to create MQD backup for ring %s\n",
|
||||
ring->name);
|
||||
|
|
@ -879,21 +917,21 @@ static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
|
|||
|
||||
static int mes_v10_1_sw_init(void *handle)
|
||||
{
|
||||
int r;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int r, pipe = AMDGPU_MES_SCHED_PIPE;
|
||||
|
||||
adev->mes.adev = adev;
|
||||
adev->mes.funcs = &mes_v10_1_funcs;
|
||||
|
||||
r = mes_v10_1_init_microcode(adev);
|
||||
r = mes_v10_1_init_microcode(adev, pipe);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = mes_v10_1_allocate_eop_buf(adev);
|
||||
r = mes_v10_1_allocate_eop_buf(adev, pipe);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = mes_v10_1_mqd_sw_init(adev);
|
||||
r = mes_v10_1_mqd_sw_init(adev, pipe);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -911,21 +949,23 @@ static int mes_v10_1_sw_init(void *handle)
|
|||
static int mes_v10_1_sw_fini(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int pipe = AMDGPU_MES_SCHED_PIPE;
|
||||
|
||||
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
|
||||
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
|
||||
|
||||
kfree(adev->mes.mqd_backup);
|
||||
kfree(adev->mes.mqd_backup[pipe]);
|
||||
|
||||
amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
|
||||
&adev->mes.ring.mqd_gpu_addr,
|
||||
&adev->mes.ring.mqd_ptr);
|
||||
|
||||
amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj,
|
||||
&adev->mes.eop_gpu_addr,
|
||||
amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
|
||||
&adev->mes.eop_gpu_addr[pipe],
|
||||
NULL);
|
||||
|
||||
mes_v10_1_free_microcode(adev);
|
||||
mes_v10_1_free_microcode(adev, pipe);
|
||||
amdgpu_ring_fini(&adev->mes.ring);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -936,7 +976,8 @@ static int mes_v10_1_hw_init(void *handle)
|
|||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
|
||||
r = mes_v10_1_load_microcode(adev);
|
||||
r = mes_v10_1_load_microcode(adev,
|
||||
AMDGPU_MES_SCHED_PIPE);
|
||||
if (r) {
|
||||
DRM_ERROR("failed to MES fw, r=%d\n", r);
|
||||
return r;
|
||||
|
|
@ -973,7 +1014,7 @@ static int mes_v10_1_hw_fini(void *handle)
|
|||
mes_v10_1_enable(adev, false);
|
||||
|
||||
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
|
||||
mes_v10_1_free_ucode_buffers(adev);
|
||||
mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue